公开(公告)号：US20190206942A1

公开(公告)日：2019-07-04

申请号：US16192220

申请日：2018-11-15

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/105 ,  H01L21/311

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US10134809B2

公开(公告)日：2018-11-20

申请号：US15612245

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L27/105 ,  H01L23/00

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20170271412A1

公开(公告)日：2017-09-21

申请号：US15612245

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/532 ,  H01L23/00 ,  H01L21/311 ,  H01L23/522 ,  H01L27/105 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20170186815A1

公开(公告)日：2017-06-29

申请号：US14998194

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/532 ,  H01L27/105 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US09608202B1

公开(公告)日：2017-03-28

申请号：US14950837

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt

IPC: H01L45/00

CPC classification number: H01L45/12 ,  H01L23/48 ,  H01L24/16 ,  H01L24/48 ,  H01L27/11526 ,  H01L45/1675 ,  H01L45/1683 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/13099 ,  H01L2224/45099

Abstract: Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of wordlines disposed in a memory region of a die, and a first fill layer deposited between adjacent wordlines of the plurality of wordlines in the memory region, to provide structural integrity for the memory array. At least a portion of a periphery region of the die adjacent to the memory region may be substantially filled with a second fill layer that is different than the first fill layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09704923B1

公开(公告)日：2017-07-11

申请号：US14998194

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Michael J. Bernhardt ,  Yudong Kim ,  Denzil S. Frost ,  Tuman Earl Allen, III ,  Kevin Lee Baker ,  Kolya Yastrebenetsky ,  Ronald Allen Weimer

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522 ,  H01L27/105

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US10607695B2

公开(公告)日：2020-03-31

申请号：US15770491

申请日：2016-09-06

Applicant: INTEL CORPORATION

Inventor： Michael J. Bernhardt

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L27/11526 ,  H01L27/22

Abstract: Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of wordlines disposed in a memory region of a die, and a first fill layer deposited between adjacent wordlines of the plurality of wordlines in the memory region, to provide structural integrity for the memory array. At least a portion of a periphery region of the die adjacent to the memory region may be substantially filled with a second fill layer that is different than the first fill layer. Other embodiments may be described and/or claimed.