公开(公告)号：US11411095B2

公开(公告)日：2022-08-09

申请号：US15859325

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Subhash Joshi ,  Michael J. Jackson ,  Michael L. Hattendorf

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

公开(公告)号：US09633835B2

公开(公告)日：2017-04-25

申请号：US14020299

申请日：2013-09-06

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Michael L. Hattendorf ,  Subhash M. Joshi

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

公开(公告)号：US09966440B2

公开(公告)日：2018-05-08

申请号：US14517365

申请日：2014-10-17

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Harold W. Kennel

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/207 ,  H01L21/285 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/267 ,  H01L21/28525 ,  H01L21/28568 ,  H01L29/165 ,  H01L29/207 ,  H01L29/42392 ,  H01L29/452 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.

公开(公告)号：US08896066B2

公开(公告)日：2014-11-25

申请号：US13685369

申请日：2012-11-26

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Harold W. Kennel

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/267 ,  H01L21/28525 ,  H01L21/28568 ,  H01L29/165 ,  H01L29/207 ,  H01L29/42392 ,  H01L29/452 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.

Abstract translation: 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用诸如硅或硅锗（SiGe）源极/漏极区域上的一种或多种金属/合金的金属接触来实现。 根据一个示例性实施例，在源极/漏极和接触金属之间设置中间锡掺杂的III-V材料层，以显着降低接触电阻。 可以使用锡掺杂层的部分或完全氧化来进一步提高接触电阻。 在一些示例情况下，锡掺杂的III-V材料层在衬底附近具有半导体相和金属接触附近的氧化物相。 根据本公开，许多晶体管配置和合适的制造工艺将是显而易见的，包括平面和非平面晶体管结构（例如，FinFET，纳米线晶体管等），以及应变和未染色的通道结构。