公开(公告)号：US20190042131A1

公开(公告)日：2019-02-07

申请号：US15940499

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Christopher E. COX ,  Navneet DOUR ,  Asaf RUBINSTEIN ,  Israel DIAMAND

IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

公开(公告)号：US20190042382A1

公开(公告)日：2019-02-07

申请号：US15857535

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Navneet DOUR ,  Christopher E. COX

IPC: G06F11/273 ,  G06F11/27 ,  G06F9/448

Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.