公开(公告)号：US20200090992A1

公开(公告)日：2020-03-19

申请号：US16582923

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Yuriy V. SHUSTERMAN ,  Flavio GRIGGIO ,  Tejaswi K. INDUKURI ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20190221478A1

公开(公告)日：2019-07-18

申请号：US16249593

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Yuriy V. SHUSTERMAN ,  Flavio GRIGGIO ,  Tejaswi K. INDUKURI ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76847 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20220157735A1

公开(公告)日：2022-05-19

申请号：US17586672

申请日：2022-01-27

Applicant: Intel Corporation

Inventor： Flavio GRIGGIO ,  Philip YASHAR ,  Anthony V. MULE ,  Gopinath TRICHY ,  Gokul MALYAVANATHAM

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US20180130707A1

公开(公告)日：2018-05-10

申请号：US15573108

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Martin M. MITAN ,  Timothy E. GLASSMAN ,  Flavio GRIGGIO ,  Grant M. KLOSTER ,  Kent N. FRASURE ,  Florian GSTREIN ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.