公开(公告)号：US08892928B2

公开(公告)日：2014-11-18

申请号：US13779862

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Christian Maciocco ,  Sameh Gobriel ,  Kristoffer Fleming ,  Gideon Prat ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  H04L29/08 ,  H04L12/12 ,  H04W52/02

CPC classification number: G06F1/3234 ,  G06F1/3209 ,  G06F1/3287 ,  H04L12/12 ,  H04L67/145 ,  H04L67/24 ,  H04W52/0206 ,  H04W76/25 ,  Y02D10/171 ,  Y02D70/1224 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162

Abstract: A system and method for maintaining connectivity between a host system running an Always-On-Always-Connected (AOAC) application and an associated remote application server. The system further includes circuitry configured to establish a communication link between the host system and the remote application server. The circuitry is configured periodically transmit keep-alive messages to the remote application server after the host system transitions to and remains in a low-power state. The keep-alive messages are configured to maintain connectivity and presence of the AOAC application with the remote application server while the host system is in the low-power state.

Abstract translation: 用于维护运行永久在线连接（AOAC）应用程序的主机系统和关联的远程应用程序服务器之间的连接的系统和方法。 该系统还包括被配置为建立主机系统和远程应用服务器之间的通信链路的电路。 在主机系统转换到并处于低功率状态之后，电路被配置为周期性地向远程应用服务器发送保持活动消息。 保持活动消息被配置为在主机系统处于低功率状态时保持与远程应用服务器的AOAC应用的连接和存在。

公开(公告)号：US10394784B2

公开(公告)日：2019-08-27

申请号：US15389218

申请日：2016-12-22

Applicant: INTEL CORPORATION

Inventor： Byron Marohn ,  Christian Maciocco ,  Sameh Gobriel ,  Ren Wang ,  Wei Shen ,  Tsung-Yuan Charlie Tai ,  Saikrishna Edupuganti

IPC: G06F16/22 ,  G06F3/06 ,  G06F16/00 ,  H04L12/701

Abstract: Technologies for managing lookup tables are described. The lookup tables may be used for a two-level lookup scheme for packet processing. When the tables need to be updated with a new key for packet processing, information about the new key may be added to a first-level lookup table and a second-level lookup table. The first-level lookup table may be used to identify a handling node for an obtained packet, and the handling node may perform a second-level table lookup to obtain information for further packet processing. The first lookup table may be replicated on all the nodes in a cluster, and the second-level lookup table may be unique to each node in the cluster. Other embodiments are described herein and claimed.

公开(公告)号：US09183144B2

公开(公告)日：2015-11-10

申请号：US13715613

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

公开(公告)号：US09176875B2

公开(公告)日：2015-11-03

申请号：US13785228

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。

公开(公告)号：US20180234336A1

公开(公告)日：2018-08-16

申请号：US15433758

申请日：2017-02-15

Applicant: Intel Corporation

Inventor： Ken Schumm ,  Sameh Gobriel ,  Asif H. Haswarey ,  Tsung-Yuan Charlie Tai

IPC: H04L12/715 ,  H04L12/703 ,  H04L12/741

CPC classification number: H04L45/46 ,  H04L45/28 ,  H04L45/745

Abstract: Apparatus and method to facilitate networked compute node cluster routing are disclosed herein. In some embodiments, a compute node for cluster compute may include one or more input ports to receive data packets from first selected ones of a cluster of compute nodes; one or more output ports to route data packets to second selected ones of the cluster of computer nodes; and one or more processors, wherein the one or more processors includes logic to determine a particular output port, of the one or more output ports, to which a data packet received at the one or more input ports is to be routed, and wherein the logic is to exclude output ports associated with links indicated in fault status information as having a fault status to be the particular output port to which the data packet is to be routed.

公开(公告)号：US10938712B2

公开(公告)日：2021-03-02

申请号：US15433758

申请日：2017-02-15

Applicant: Intel Corporation

Inventor： Ken Schumm ,  Sameh Gobriel ,  Asif H. Haswarey ,  Tsung-Yuan Charlie Tai

IPC: H04L12/703 ,  H04L12/715 ,  H04L12/741

Abstract: Apparatus and method to facilitate networked compute node cluster routing are disclosed herein. In some embodiments, a compute node for cluster compute may include one or more input ports to receive data packets from first selected ones of a cluster of compute nodes; one or more output ports to route data packets to second selected ones of the cluster of computer nodes; and one or more processors, wherein the one or more processors includes logic to determine a particular output port, of the one or more output ports, to which a data packet received at the one or more input ports is to be routed, and wherein the logic is to exclude output ports associated with links indicated in fault status information as having a fault status to be the particular output port to which the data packet is to be routed.