公开(公告)号：US10817454B2

公开(公告)日：2020-10-27

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3228

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

公开(公告)号：US20190251055A1

公开(公告)日：2019-08-15

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3228 ,  G06F1/3234 ,  G06F9/38

CPC classification number: G06F13/4068 ,  G06F1/3228 ,  G06F1/3253 ,  G06F1/329 ,  G06F9/3877 ,  G06F13/4221 ,  G06F2212/1028

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.