公开(公告)号：US20240070366A1

公开(公告)日：2024-02-29

申请号：US17895107

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Nicholas HAEHN ,  Raquel DE SOUZA BORGES FERREIRA ,  Siddharth ALUR ,  Prakaram JOSHI ,  Dhanya ATHREYA ,  Yidnekachew MEKONNEN ,  Ali HARIRI ,  Andrea NICOLAS ,  Sri Chaitra Jyotsna CHAVALI ,  Kemal AYGUN

IPC: G06F30/392 ,  H01L23/498

CPC classification number: G06F30/392 ,  H01L23/49838 ,  G06F2119/22 ,  H01L23/49822

Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.

公开(公告)号：US20240061987A1

公开(公告)日：2024-02-22

申请号：US17889405

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Prakaram JOSHI ,  Todd SNIDER ,  Srinivas MOOLA

IPC: G06F30/398

CPC classification number: G06F30/398 ,  G06F2113/18

Abstract: A method of semiconductor modelling includes determining for a virtual model of a layer of a semiconductor package, wherein the layer includes a metal layer, one or more first regions of the layer that do not satisfy a first layer design rule; adding first voids to the one or more first regions to satisfy the first layer design rule; determining for the layer including the metal pattern and the first voids, one or more second regions of the layer that do not satisfy a second layer design rule, different from the first layer design rule; and adding second voids to the one or more second regions to satisfy the second layer design rule.

公开(公告)号：US20220126210A1

公开(公告)日：2022-04-28

申请号：US17078038

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Gaurav KUMAR ,  Scott JANUS ,  Prakaram JOSHI ,  Changliang L. WANG

IPC: A63F13/75 ,  A63F13/71 ,  A63F13/352 ,  G06T15/00 ,  G06T17/20

Abstract: Examples described herein relate to a system that includes a central processing unit; a trusted execution environment (TEE); and a graphics processing system. In some examples, the central processing unit is to process homomorphically encrypted video game object data. In some examples, the TEE is to transpose the processed homomorphically encrypted object data to a second encryption format. In some examples, the graphics processing system is to perform a graphics processing pipeline operation on the object data in the second encryption format and provide rendered image data of the video game to a buffer. In some examples, the TEE is to receive homomorphic decryption keys and transpose the processed homomorphically encrypted object data to a second encryption format based on the homomorphic decryption keys. In some examples, the system is to inform a gaming server of a change to object data received from the gaming server to identify cheating.