公开(公告)号：US20190341342A1

公开(公告)日：2019-11-07

申请号：US15970602

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Digvijay RAORANE ,  Yidnekachew MEKONNEN

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments include packages substrates and a method of forming the package substrate. A package substrate includes a first dielectric comprising a first conductive layer, and a second dielectric comprising a second conductive layer and a third conductive layer. The second and third conductive layers are embedded in the second dielectric, where a top surface of the third conductive layer is above a top surface of the second conductive layer. The package substrate has a fourth conductive layer on the second dielectric. The first dielectric has a first dielectric thickness between the first and third conductive layers. The first dielectric also has a second dielectric thickness between the first and second conductive layers. The package substrate includes the second dielectric thickness that is greater than the first dielectric thickness. The second dielectric may have a z-height of a first bottom surface greater than a z-height of a second bottom surface.

公开(公告)号：US20220157706A1

公开(公告)日：2022-05-19

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US20180226310A1

公开(公告)日：2018-08-09

申请号：US15748138

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Feras EID ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Yidnekachew MEKONNEN ,  Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Aleksandar ALEKSOV ,  Nathan FRITZ

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/473 ,  H01L23/538 ,  H01L23/492

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/12 ,  H01L23/473 ,  H01L23/492 ,  H01L23/5389

Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.

公开(公告)号：US20240070366A1

公开(公告)日：2024-02-29

申请号：US17895107

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Nicholas HAEHN ,  Raquel DE SOUZA BORGES FERREIRA ,  Siddharth ALUR ,  Prakaram JOSHI ,  Dhanya ATHREYA ,  Yidnekachew MEKONNEN ,  Ali HARIRI ,  Andrea NICOLAS ,  Sri Chaitra Jyotsna CHAVALI ,  Kemal AYGUN

IPC: G06F30/392 ,  H01L23/498

CPC classification number: G06F30/392 ,  H01L23/49838 ,  G06F2119/22 ,  H01L23/49822

Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.

公开(公告)号：US20200381350A1

公开(公告)日：2020-12-03

申请号：US16636620

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.