公开(公告)号：US09916988B2

公开(公告)日：2018-03-13

申请号：US14914627

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Shakuntala Sundararajan ,  Nadia Rahhal-Orabi ,  Leonard P Guler ,  Michael Harper ,  Ralph Thomas Troeger

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/31051 ,  H01L21/76814 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/401

Abstract: Techniques and structures for protecting etched features during etch mask removal. In embodiments, a mask is patterned and a substrate layer etched to transfer the pattern. Subsequent to etching the substrate layer, features patterned into the substrate are covered with a sacrificial material backfilling the etch mask. At least a top portion of the mask is removed with the substrate features protected by the sacrificial material. The sacrificial material and any remaining portion of the mask are then removed. In further embodiments, a gate contact opening etched into a substrate layer is protected with a sacrificial material having the same composition as a first material layer of a multi-layered etch mask. A second material layer of the etch mask having a similar composition as the substrate layer is removed before subsequently removing the sacrificial material concurrently with the first mask material layer.

公开(公告)号：US12170319B2

公开(公告)日：2024-12-17

申请号：US17033362

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin Cook ,  Anand S. Murthy ,  Gilbert Dewey ,  Nazila Haratipour ,  Ralph Thomas Troeger ,  Christopher J. Jezewski ,  I-Cheng Tung

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.