公开(公告)号：US20180196612A1

公开(公告)日：2018-07-12

申请号：US15860648

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Ravi J. Kumar

IPC: G06F3/06 ,  G11C29/52 ,  G11C29/50 ,  G11C29/02 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C11/56 ,  G06F11/20 ,  G06F11/10 ,  G11C16/00 ,  G11C29/04

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

公开(公告)号：US09857992B2

公开(公告)日：2018-01-02

申请号：US15076963

申请日：2016-03-22

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Ravi J. Kumar

IPC: G11C29/02 ,  G11C29/50 ,  G11C29/10 ,  G11C29/04 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G11C11/56 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C16/00

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160357458A1

公开(公告)日：2016-12-08

申请号：US15076963

申请日：2016-03-22

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Ravi J. Kumar

IPC: G06F3/06 ,  G11C16/14 ,  G11C29/52 ,  G11C11/56 ,  G06F11/20 ,  G06F11/10 ,  G11C16/34 ,  G11C16/26

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了提供动态窗口以提高NAND（Not And）存储器耐久性的方法和装置。 在一个实施例中，与NAND存储器件相关联的编程擦除窗口通过从较高的擦除验证（TEV）电压开始并基于当前周期在NAND存储器件的使用寿命内随后的周期降低TEV电压而动态地改变 计数值。 或者，通过以更高的擦除验证（PV）电压和擦除验证（TEV）电压开始，并且基于当前的NAND存储器件的使用寿命期间的随后的周期来降低PV和TEV电压，编程擦除窗口被动态变化 循环计数值。 还公开并要求保护其他实施例。