公开(公告)号：US20180286874A1

公开(公告)日：2018-10-04

申请号：US15477051

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Scott M. Pook

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11543 ,  H01L21/02 ,  H01L29/68 ,  G11C16/10 ,  G11C16/04

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/02587 ,  H01L27/11582

Abstract: Conductive channel technology is disclosed. In one example, a memory component can include a source line, a conductive channel having first and second conductive layers electrically coupled to the source line and memory cells adjacent to the conductive channel. In one aspect, channel conductivity and reliability is improved over a single layer conductive channel formation scheme by preventing unwanted oxide formation, increasing the interface contact area, and by modulating material grain size and boundaries via multiple thin channel integration scheme. Associated systems and methods are also disclosed.

公开(公告)号：US10269824B2

公开(公告)日：2019-04-23

申请号：US15477051

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Scott M. Pook

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/02 ,  G11C16/10 ,  G11C16/04

Abstract: Conductive channel technology is disclosed. In one example, a memory component can include a source line, a conductive channel having first and second conductive layers electrically coupled to the source line and memory cells adjacent to the conductive channel. In one aspect, channel conductivity and reliability is improved over a single layer conductive channel formation scheme by preventing unwanted oxide formation, increasing the interface contact area, and by modulating material grain size and boundaries via multiple thin channel integration scheme. Associated systems and methods are also disclosed.