Phase-locked loop circuit with improved performance
    1.
    发明授权
    Phase-locked loop circuit with improved performance 有权
    锁相环电路具有改进的性能

    公开(公告)号:US09294104B2

    公开(公告)日:2016-03-22

    申请号:US14332614

    申请日:2014-07-16

    Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

    Abstract translation: 锁相环电路包括相位检测器,电荷泵,电容器和电容器倍增器。 相位检测器接收参考频率和反馈频率以产生上/下信号。 包括正节点和负节点的电荷泵接收上/下信号以产生第一电流。 电容器耦合到负节点。 耦合到负节点的电容器倍增器产生第二电流,其是第一电流除以第一缩放数。

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