公开(公告)号：US09784770B2

公开(公告)日：2017-10-10

申请号：US14287569

申请日：2014-05-27

Applicant: Intel Corporation

Inventor： Shih-An Yu ,  Yu-Hong Lin ,  Sen-You Liu ,  Fang-Ren Liao

IPC: H03L7/18 ,  G01R19/10 ,  G01R23/02 ,  G01R27/28 ,  H03L7/099 ,  G01R19/00 ,  H03L7/183

CPC classification number: G01R19/10 ,  G01R19/0023 ,  G01R23/02 ,  G01R27/28 ,  H03L7/099 ,  H03L7/183

Abstract: A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

公开(公告)号：US09621174B2

公开(公告)日：2017-04-11

申请号：US14709712

申请日：2015-05-12

Applicant: Intel Corporation

Inventor： Fang-Ren Liao ,  Shih-An Yu

IPC: H03L7/00 ,  H03L7/24 ,  H03B5/12 ,  H03L7/099

CPC classification number: H03L7/24 ,  H03B5/1265 ,  H03B2200/005 ,  H03B2201/011 ,  H03B2201/025 ,  H03L7/099

Abstract: A frequency calibration method for calibrating an output frequency of a voltage-controlled oscillator is provided. The voltage-controlled oscillator includes a first capacitor bank, a second capacitor bank, and a third capacitor bank. The first capacitor bank and the third capacitor bank are initially disabled and the second capacitor bank is initially enabled. The method includes, when the initial output frequency is lower than a reference frequency, adjusting the capacitance of the second capacitor bank until the calibrated output frequency is greater than the reference frequency, and when the initial output frequency is greater than the reference frequency, enabling the first capacitor bank and gradually increasing the capacitance of the first capacitor bank until the calibrated output frequency is lower than the reference frequency.

公开(公告)号：US09294104B2

公开(公告)日：2016-03-22

申请号：US14332614

申请日：2014-07-16

Applicant: Intel Corporation

Inventor： Shih-An Yu ,  Sen-You Liu ,  Fang-Ren Liao ,  Yi-Pei Su

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/093 ,  H03L7/18 ,  H03L7/08 ,  H03L7/099 ,  H03B5/32 ,  H02M3/07

CPC classification number: H03B5/32 ,  H02M3/07 ,  H03C3/0933 ,  H03L7/087 ,  H03L7/0893 ,  H03L7/18 ,  H03L7/1972 ,  H03L7/1976

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract translation: 锁相环电路包括相位检测器，电荷泵，电容器和电容器倍增器。 相位检测器接收参考频率和反馈频率以产生上/下信号。 包括正节点和负节点的电荷泵接收上/下信号以产生第一电流。 电容器耦合到负节点。 耦合到负节点的电容器倍增器产生第二电流，其是第一电流除以第一缩放数。