公开(公告)号：US09753531B2

公开(公告)日：2017-09-05

申请号：US14603955

申请日：2015-01-23

申请人： Intel Corporation

发明人： Sanjeev S. Jahagirdar ,  Ryan Wells ,  Inder Sodhi

IPC分类号： G06F1/32 ,  G06F13/24

CPC分类号： G06F1/3293 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F13/24 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

公开(公告)号：US09292068B2

公开(公告)日：2016-03-22

申请号：US13782539

申请日：2013-03-01

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F13/00 ,  G06F1/32 ,  G06F1/26 ,  G06F9/38

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

公开(公告)号：US20160026229A1

公开(公告)日：2016-01-28

申请号：US14875930

申请日：2015-10-06

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

公开(公告)号：US09618997B2

公开(公告)日：2017-04-11

申请号：US14565723

申请日：2014-12-10

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F9/38

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

公开(公告)号：US20150095673A1

公开(公告)日：2015-04-02

申请号：US14565723

申请日：2014-12-10

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessmann ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有功率控制器以控制处理器工作频率的多核处理器。 更具体地，功率控制器可以将处理器的最大工作频率限制在小于配置的最大工作频率，以便能够减少响应于电力状态事件而发生的频率转换的数量，从而避免在处理这些操作时所执行的操作的开销 转换 描述和要求保护其他实施例。

公开(公告)号：US20190212801A1

公开(公告)日：2019-07-11

申请号：US16249103

申请日：2019-01-16

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/324 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3293 ,  G06F1/3296 ,  G11C7/22 ,  G06F1/3203

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US09354692B2

公开(公告)日：2016-05-31

申请号：US14451807

申请日：2014-08-05

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/26 ,  G06F1/32 ,  G11C7/22

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。

公开(公告)号：US20150199002A1

公开(公告)日：2015-07-16

申请号：US14603955

申请日：2015-01-23

申请人： Intel Corporation

发明人： Sanjeev S. Jahagirdhar ,  Ryan Wells ,  Inder Sodhi

IPC分类号： G06F1/32 ,  G06F13/24

CPC分类号： G06F1/3293 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F13/24 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

摘要翻译： 处理器可以确定驻留在省电状态的非核心域的实际驻留时间，并且基于处理器可以确定处理器的最佳省电状态（P状态）的实际驻留时间。 响应于非核心域进入省电状态，中断发生器（IG）可以产生第一中断，并且设备驱动器或操作系统可以使用第一中断来启动定时器（第一值）。 响应于退出省电状态的非核心域，IG可以产生第二中断，并且设备驱动器或操作系统可以使用第二中断来停止定时器（最终值）。 电源管理单元可以使用最终和第一个值来确定实际的驻留时间。

公开(公告)号：US10248181B2

公开(公告)日：2019-04-02

申请号：US15381241

申请日：2016-12-16

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/32 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3203 ,  G11C7/22 ,  G06F13/42 ,  G06F1/3296 ,  G06F13/40

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US10037067B2

公开(公告)日：2018-07-31

申请号：US15138505

申请日：2016-04-26

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/26 ,  G06F1/32 ,  G11C7/22 ,  G06F13/42 ,  G06F13/40

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.