公开(公告)号：US20250106997A1

公开(公告)日：2025-03-27

申请号：US18373088

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Ehsan ZAMANI ,  Umesh PRASAD ,  Logan MYERS ,  Shayan KAVIANI ,  Darko GRUJICIC ,  Elham TAVAKOLI ,  Mahdi MOHAMMADIGHALENI ,  Rengarajan SHANMUGAM ,  Rachel Guia GIRON ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN

IPC: H05K1/11 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03

Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a substrate that is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, and a liner with a first surface is on a sidewall of the opening and a second surface is facing away from the sidewall of the opening. In an embodiment, the liner comprises a matrix, and filler particles in the matrix. In an embodiment, a plurality of cavities are provided into the second surface of the liner. In an embodiment, a via is in the opening, where the via is electrically conductive.

公开(公告)号：US20240213301A1

公开(公告)日：2024-06-27

申请号：US18089471

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Thomas L. SOUNART ,  Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Shayan KAVIANI ,  Suddhasattwa NAD ,  Mahdi MOHAMMADIGHALENI ,  Marcel WALL ,  Rengarajan SHANMUGAM

IPC: H01G4/33

CPC classification number: H01L28/40 ,  H01G4/33

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.