公开(公告)号：US20240188222A1

公开(公告)日：2024-06-06

申请号：US18060595

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Darko GRUJICIC ,  Marcel WALL ,  Jason STEILL

IPC: H05K3/22 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/225 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0029 ,  H01L21/486

Abstract: The present disclosure is directed to a method providing a substrate core having a glass core layer with top and bottom surfaces and a build-up process performing operations to form a plurality of through-glass vias formed through the glass core layer and a plurality of conductive layers on the top and bottom surfaces of the glass core layer. As an integral part of the build-up process, a defect detection method may be used to detect defects in the glass core layer. The inspection for defects may be performed after selected operations. After one or more defect (e.g., crack) is uncovered, a repair process may be performed to repair the defects in the glass core layer. The repair of a defect may be performed immediately upon detection or after selected operations as a comprehensive repair of a group of defects.

公开(公告)号：US20220010452A1

公开(公告)日：2022-01-13

申请号：US17482513

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chandrasekharan NAIR ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Srinivasan RAMAN ,  Roy DITTLER ,  Daniel SOWA ,  Robert BARESEL, II ,  Marcel WALL ,  Rahul MANEPALLI

IPC: C25D17/06 ,  C25D17/12 ,  C25D17/00 ,  H01L21/67

Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

公开(公告)号：US20230420322A1

公开(公告)日：2023-12-28

申请号：US17848615

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Yi YANG ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Darko GRUJICIC ,  Marcel WALL

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L23/3142 ,  H01L23/49827 ,  H01L23/49513

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an organic adhesion promoter layer on the surface of a copper trace to reduce delamination between a dielectric material and the surface of the copper trace, and to facilitate a smooth surface interface between the surface of the copper trace and of a copper feature, such as a copper-filled via, placed on the surface of the copper trace. The smooth surface interface reduces insertion loss and enables routing of higher frequency signals on a package, and does not require roughing of the copper trace in order to adhere to the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317614A1

公开(公告)日：2023-10-05

申请号：US17707351

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Marcel WALL ,  Benjamin DUONG

IPC: H01L23/532 ,  H05K1/03 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/5329 ,  H05K1/036 ,  H05K1/111 ,  H01L23/53228 ,  H01L21/4857 ,  H01L21/486 ,  H05K2201/0145 ,  H05K2201/0195

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate, and a second layer is over the trace, where the second layer comprises silicon and nitrogen. In an embodiment, the second layer is chemically bonded to the one of the first layers

公开(公告)号：US20230091666A1

公开(公告)日：2023-03-23

申请号：US17482399

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Aleksandar ALEKSOV ,  Helme A. CASTRO DE LA TORRE ,  Kristof DARMAWIKARTA ,  Darko GRUJICIC ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Rengarajan SHANMUGAM ,  Thomas L. SOUNART ,  Marcel WALL

IPC: H05K1/18 ,  H05K1/03 ,  H01G4/33 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20200312768A1

公开(公告)日：2020-10-01

申请号：US16366647

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Marcel WALL

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48

Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.

公开(公告)号：US20190320537A1

公开(公告)日：2019-10-17

申请号：US15954040

申请日：2018-04-16

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H05K3/38 ,  H01L21/027 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03

Abstract: Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

公开(公告)号：US20240213131A1

公开(公告)日：2024-06-27

申请号：US18089499

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Yi YANG ,  Andrew WENTZEL ,  Marcel WALL ,  Suddhasattwa NAD

IPC: H01L23/498 ,  C25D3/38 ,  C25D7/12 ,  C25D17/00 ,  H01L23/15

CPC classification number: H01L23/49827 ,  C25D3/38 ,  C25D7/12 ,  C25D17/001 ,  H01L23/15 ,  H01L24/16 ,  H01L2224/16225

Abstract: In an embodiment, a package substrate is described. In an embodiment, the package substrate comprises a layer, where the layer is a dielectric material. In an embodiment, a via opening is provided through a thickness of the layer. In an embodiment, a conductive via is in the via opening, where the conductive via has a substantially uniform composition throughout a thickness of the conductive via. In an embodiment the conductive via directly contacts the layer.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20200315023A1

公开(公告)日：2020-10-01

申请号：US16363925

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kassandra NIKKHAH ,  Joshua MICHALAK ,  Marcel WALL ,  Rahul MANEPALLI ,  Cemil GEYIK ,  Benjamin DUONG ,  Darko GRUJICIC

IPC: H05K3/10 ,  H01L23/538 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.