公开(公告)号：US20230091666A1

公开(公告)日：2023-03-23

申请号：US17482399

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Aleksandar ALEKSOV ,  Helme A. CASTRO DE LA TORRE ,  Kristof DARMAWIKARTA ,  Darko GRUJICIC ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Rengarajan SHANMUGAM ,  Thomas L. SOUNART ,  Marcel WALL

IPC: H05K1/18 ,  H05K1/03 ,  H01G4/33 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20240176167A1

公开(公告)日：2024-05-30

申请号：US18071246

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Tolga ACIKALIN ,  Harel FRISH ,  Sandeep GAAN ,  John HECK ,  Eric J. M. MORET ,  Suddhasattwa NAD ,  Haisheng RONG

IPC: G02F1/01 ,  G02B6/125

CPC classification number: G02F1/0113 ,  G02B6/125 ,  G02F1/0147 ,  G02B2006/12145

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core where the core comprises glass. In an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.

公开(公告)号：US20240079530A1

公开(公告)日：2024-03-07

申请号：US17903126

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Nicholas HAEHN ,  Andrea NICOLAS FLORES ,  Ali LEHAF ,  Benjamin DUONG ,  Joshua STACEY

IPC: H01L33/48 ,  H01L33/00 ,  H01L33/60 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L33/005 ,  H01L33/60 ,  H01L33/62 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20200315023A1

公开(公告)日：2020-10-01

申请号：US16363925

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kassandra NIKKHAH ,  Joshua MICHALAK ,  Marcel WALL ,  Rahul MANEPALLI ,  Cemil GEYIK ,  Benjamin DUONG ,  Darko GRUJICIC

IPC: H05K3/10 ,  H01L23/538 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

公开(公告)号：US20240312888A1

公开(公告)日：2024-09-19

申请号：US18121264

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317614A1

公开(公告)日：2023-10-05

申请号：US17707351

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Marcel WALL ,  Benjamin DUONG

IPC: H01L23/532 ,  H05K1/03 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/5329 ,  H05K1/036 ,  H05K1/111 ,  H01L23/53228 ,  H01L21/4857 ,  H01L21/486 ,  H05K2201/0145 ,  H05K2201/0195

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate, and a second layer is over the trace, where the second layer comprises silicon and nitrogen. In an embodiment, the second layer is chemically bonded to the one of the first layers

公开(公告)号：US20240312853A1

公开(公告)日：2024-09-19

申请号：US18121331

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213301A1

公开(公告)日：2024-06-27

申请号：US18089471

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Thomas L. SOUNART ,  Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Shayan KAVIANI ,  Suddhasattwa NAD ,  Mahdi MOHAMMADIGHALENI ,  Marcel WALL ,  Rengarajan SHANMUGAM

IPC: H01G4/33

CPC classification number: H01L28/40 ,  H01G4/33

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.