公开(公告)号：US20190081630A1

公开(公告)日：2019-03-14

申请号：US16184794

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Shenggao LI ,  Stefan RUSU

IPC: H03L7/00 ,  G06F13/40 ,  H03L7/091 ,  H01L25/065 ,  G06F1/12 ,  H03L7/081 ,  H03L7/07 ,  H04L7/00 ,  H01L23/48

CPC classification number: H03L7/00 ,  G06F1/12 ,  G06F13/4027 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2225/06541 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0012 ,  H04L7/0025 ,  Y02D10/14 ,  Y02D10/151

Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

公开(公告)号：US20180167240A1

公开(公告)日：2018-06-14

申请号：US15372851

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Shenggao LI ,  Ji CHEN

IPC: H04L25/03 ,  H04B1/16 ,  H04L1/00

CPC classification number: H04L25/03057 ,  H04B1/123 ,  H04B1/16 ,  H04L1/0036 ,  H04L25/0272 ,  H04L25/0296 ,  H04L25/061 ,  H04L25/063

Abstract: An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.

公开(公告)号：US20160315642A1

公开(公告)日：2016-10-27

申请号：US15084329

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Shenggao LI ,  Xiaoqing WANG

IPC: H04B1/04 ,  H04L25/02 ,  H04B10/50 ,  H04L25/03

CPC classification number: H04B1/0475 ,  H04B10/503 ,  H04L25/0272 ,  H04L25/03878

Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.