公开(公告)号：US20230178158A1

公开(公告)日：2023-06-08

申请号：US17545672

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Soo-yong Park ,  Pranav Chava ,  Binh Ngo

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.

公开(公告)号：US11653496B2

公开(公告)日：2023-05-16

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Chuan Lin ,  Deepak Thimmegowda ,  Zengtao Liu ,  Binh N. Ngo ,  Soo-yong Park

IPC: H01L27/11 ,  H01L27/1158 ,  H01L29/10 ,  G11C16/04

CPC classification number: H01L27/1158 ,  G11C16/0466 ,  G11C16/0483 ,  H01L29/1033

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.