公开(公告)号：US11653496B2

公开(公告)日：2023-05-16

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Chuan Lin ,  Deepak Thimmegowda ,  Zengtao Liu ,  Binh N. Ngo ,  Soo-yong Park

IPC: H01L27/11 ,  H01L27/1158 ,  H01L29/10 ,  G11C16/04

CPC classification number: H01L27/1158 ,  G11C16/0466 ,  G11C16/0483 ,  H01L29/1033

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

公开(公告)号：US11500446B2

公开(公告)日：2022-11-15

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Shankar Natarajan ,  Chang Wan Ha ,  Chee Law ,  Khaled Hasnat ,  Chuan Lin ,  Shafqat Ahmed

IPC: G06F1/32 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F1/3234

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.