公开(公告)号：US20180068695A1

公开(公告)日：2018-03-08

申请号：US15703589

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant S. DAMLE ,  Frank T. HADY ,  Paul D. RUBY ,  Kiran PANGAL ,  Sowmiya JAYACHANDRAN

IPC: G11C7/10 ,  G11C11/406 ,  G11C16/34

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

公开(公告)号：US20170286287A1

公开(公告)日：2017-10-05

申请号：US15089315

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Frank T. HADY

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a plurality of consecutive logical addresses is received and a determination is made of consecutive physical blocks comprising a block group. Each of the physical blocks has data for a plurality of the consecutive logical addresses. The sequential write data is written to consecutive physical data locations having data for the determined consecutive physical blocks of the block group. The block group metadata for the block group is updated.

公开(公告)号：US20170337009A1

公开(公告)日：2017-11-23

申请号：US15640373

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Blaise FANNING ,  Shekoufeh QAWAMI ,  Raymond S. Tetrick ,  Frank T. HADY

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

公开(公告)号：US20240378150A1

公开(公告)日：2024-11-14

申请号：US18781854

申请日：2024-07-23

Applicant: Intel Corporation

Inventor： Frank T. HADY ,  Sanjeev N. TRIKA

IPC: G06F12/0815 ,  G06F8/41 ,  G06F12/0804

Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.

公开(公告)号：US20200226067A1

公开(公告)日：2020-07-16

申请号：US16828700

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Frank T. HADY ,  Sanjeev N. TRIKA

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F8/41

Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.

公开(公告)号：US20190286356A1

公开(公告)日：2019-09-19

申请号：US16363576

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Blaise FANNING ,  Shekoufeh QAWAMI ,  Raymond S. TETRICK ,  Frank T. HADY

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02 ,  G11C16/00 ,  G11C7/10 ,  G06F12/08 ,  G06F12/1009

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

公开(公告)号：US20180004688A1

公开(公告)日：2018-01-04

申请号：US15201370

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Emily CHUNG ,  Frank T. HADY ,  George VERGIS

IPC: G06F13/16 ,  G11C11/4076 ,  G06F13/42 ,  G11C11/4093 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/42 ,  G11C7/1066 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/32 ,  G11C2207/2254

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

公开(公告)号：US20170286014A1

公开(公告)日：2017-10-05

申请号：US15089333

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Frank T. HADY

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/16

Abstract: Provided are an apparatus and method for processing sequential writes portions of an addressable unit memory dies to store data. A write to a first portion of an addressable unit is received and the write is written to the first portion of the addressable unit. A next write is received to a next portion of the addressable unit following a previous write to a previous portion of the addressable unit. The next write is written to the next portion of the addressable unit sequentially following the previous portion in response to the next write being sequential with respect to the previous write. Data other than the next write is written to the addressable unit following the previous portion in response to the next write not being sequential with respect to the previous write.