公开(公告)号：US10365708B2

公开(公告)日：2019-07-30

申请号：US15379283

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Simon N. Peffers ,  Sean M. Gulley ,  Thomas L. Dmukauskas ,  Aaron Gorius ,  Vinodh Gopal

IPC: G06F11/24 ,  G06F1/3296 ,  G01R31/28 ,  G06F1/324 ,  G06F1/3206

Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.

公开(公告)号：US20180164864A1

公开(公告)日：2018-06-14

申请号：US15379283

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Simon N. Peffers ,  Sean M. Gulley ,  Thomas L. Dmukauskas ,  Aaron Gorius ,  Vinodh Gopal

IPC: G06F1/28 ,  G01R31/28 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G01R31/2856 ,  G01R31/2874 ,  G01R31/2879 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/24 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.