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公开(公告)号：US10598696B2
公开(公告)日：2020-03-24
申请号：US15083082
申请日：2016-03-28
Applicant: INTEL CORPORATION
Inventor： Joseph D. Stanford , David Craig , Todd P. Albertson , Mohit Mamodia , Dingying Xu
Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
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公开(公告)号：US11112430B2
公开(公告)日：2021-09-07
申请号：US16366197
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Anil Kaza , Donald E. Edenfeld , Todd P. Albertson , Patrick Whiting
Abstract: A probe head may be utilized to test an electronic device. The probe head may include a probe axis extending along a length of the probe head. The probe head may include a probe core including a first metal. The probe core may include a core surface having a first dimension. The first dimension may be perpendicular to the probe axis. The probe core may include a probe tip, for instance extending from the core surface along the probe axis. The probe tip has a second dimension that may be perpendicular to the probe axis. The second dimension may be less than the first dimension of the core surface. The probe head may include a cladding layer that includes a second metal. The cladding layer may be coupled around a perimeter of the probe core. The probe tip may extend beyond the cladding layer.
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公开(公告)号：US20160274148A1
公开(公告)日：2016-09-22
申请号：US15165984
申请日：2016-05-26
Applicant: Intel Corporation
Inventor： Kip Stevenson , Todd P. Albertson , David Shia , Kamil Salloum
CPC classification number: G01R1/06755 , G01R3/00 , G01R31/26 , G01R31/2886
Abstract: An examples includes a substrate, including a conductive trace and a layer disposed on top of the conductive trace, the layer defining at least one cavity extending to the conductive trace and an electrical probe disposed in the cavity, with solder coupling the electrical probe to the conductive trace. The electrical probe can include a high yield strength wire core including a refractory metal and a thin oxidation protection layer concentrically disposed around high yield strength wire core and providing an outside surface of the electrical probe, the thin oxidation protection layer including predominantly one or more materials selected from gold, platinum, ruthenium, rhodium, palladium, osmium, iridium, chromium, and combinations thereof, wherein the solder fills the cavity and is coupled to the electrical probe inside the cavity, disposed between the electrical probe and the layer.
Abstract translation: 示例包括基板，其包括导电迹线和设置在导电迹线顶部上的层，该层限定延伸到导电迹线的至少一个空腔和设置在该空腔中的电探针，其中焊料将电探针耦合到 导电痕迹 电探针可以包括高屈服强度的线芯，包括耐火金属和同心地设置在高屈服强度线芯周围的薄氧化保护层，并提供电探针的外表面，薄氧化保护层主要包括一种或多种材料 选自金，铂，钌，铑，钯，锇，铱，铬及其组合，其中焊料填充空腔并且耦合到设置在电探针和层之间的腔内的电探针。
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公开(公告)号：US09977054B2
公开(公告)日：2018-05-22
申请号：US14739241
申请日：2015-06-15
Applicant: INTEL CORPORATION
Inventor： Todd P. Albertson , David M. Craig , David Shia , Joseph D. Stanford
CPC classification number: G01R1/07314 , G01R1/06755
Abstract: Etching for probe wire tip is described particularly well suited to microelectronic device test. In one example, wires of a probe head are covered with an encapsulation material, the wires being attached to a test probe head substrate, each of the wires having two ends, the first end being attached to the substrate and the second end being opposite the substrate, each wire having an outer coating around a core. The wires are etched to remove the outer coating at the second end of the wires. The encapsulation material is then removed.
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公开(公告)号：US09823273B2
公开(公告)日：2017-11-21
申请号：US13931866
申请日：2013-06-29
Applicant: INTEL CORPORATION
Inventor： Keith J. Martin , Kip P. Stevenson , Kamil S. Salloum , Todd P. Albertson
CPC classification number: G01R3/00 , G01R1/06738 , Y10T29/49124
Abstract: Probe tip formation is described for die sort and test. In one example, the tips of wires of a test probe head are prepared for use as test probes. The wires are attached to a test probe head substrate. The end opposite the substrate has a tip. The tips of the wires are polished when attached to the test probe head to form a sharpened point.
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Patent Agency Ranking
6.发明授权Micro positioning test socket and methods for active precision alignment and co-planarity feedback 有权微定位测试插座和主动精密对准和共平面反馈的方法公开(公告)号：US09255945B2
公开(公告)日：2016-02-09
申请号：US14202291
申请日：2014-03-10
Applicant: Intel Corporation
Inventor： Abram M. Detofsky , Todd P. Albertson , David Shia
CPC classification number: G01R1/0408 , G01B7/31 , G01R1/0483 , G01R1/06794 , G01R31/2891 , H05K1/0268 , H05K2203/162 , H05K2203/166
Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.
Abstract translation: 描述了用于测试微电子封装结构/器件的方法和结构。 这些方法可以包括将设备放置在浮动载体中，其中浮动载体通过设置在插座壳体的四个角落中的销钉联接到插座壳体，并且其中至少两个致动马达设置在插座壳体内，并且微型 通过利用电容耦合或光纤对准系统来调节装置，其中设置在插座壳体中的对准结构和设置在装置内的对准封装球之间的最大测量电容或最大测量强度表示装置的最佳对准。 方法还包括通过使用电容耦合技术进行有源共平面检测的方法。
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公开(公告)号：US11340258B2
公开(公告)日：2022-05-24
申请号：US16817480
申请日：2020-03-12
Applicant: INTEL CORPORATION
Inventor： Joseph D. Stanford , David Craig , Todd P. Albertson , Mohit Mamodia , Dingying Xu
Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
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公开(公告)号：US20200209280A1
公开(公告)日：2020-07-02
申请号：US16817480
申请日：2020-03-12
Applicant: INTEL CORPORATION
Inventor： Joseph D. Stanford , David Craig , Todd P. Albertson , Mohit Mamodia , Dingying Xu
Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
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公开(公告)号：US20160178663A1
公开(公告)日：2016-06-23
申请号：US14581508
申请日：2014-12-23
Applicant: INTEL CORPORATION
Inventor： Mohanraj Prabhugoud , Youngseok Oh , Joseph F. Walczyk , Todd P. Albertson
CPC classification number: G01R1/07357 , G01R1/0466 , G01R1/0483
Abstract: A test die contactor is described with a formed wire probe interconnect. In one example the contactor includes a plurality of wire probes formed to be resilient against longitudinal pressure, a first aligner proximate one end of the wire probes having a first plurality of holes through which the wire probes extend, the first alignment layer to align the wire probes to contact pads of a text fixture, a second aligner proximate the other end of the wire probes having a second plurality of holes through the wire probes extend, the second alignment layer to align the wire probes to contact pads of a device under test, and an insulating layer between the first and the second aligner through which the wire probes extend to hold the wire probes when compressed by longitudinal pressure.
Abstract translation: 使用形成的导线探针互连来描述测试模具接触器。 在一个示例中，接触器包括形成为抵抗纵向压力弹性的多个线探针，靠近线探头的一端的第一对准器具有第一多个孔，线探针延伸穿过该第一多个孔，第一对准层对准线 探针到文本夹具的接触垫，靠近导线探针的另一端的第二对准器具有穿过线探头的第二多个孔延伸，第二对准层将线探针对准待测器件的接触垫， 以及在第一和第二对准器之间的绝缘层，当通过纵向压力压缩时，线探针延伸通过该绝缘层保持线探头。
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公开(公告)号：US09354273B2
公开(公告)日：2016-05-31
申请号：US13725255
申请日：2012-12-21
Applicant: Intel Corporation
Inventor： Kip Stevenson , Todd P. Albertson , David Shia , Kamil Salloum
CPC classification number: G01R1/06755 , G01R3/00 , G01R31/26 , G01R31/2886
Abstract: An examples includes a substrate, including a conductive trace and a layer disposed on top of the conductive trace, the layer defining at least one cavity extending to the conductive trace and an electrical probe disposed in the cavity, with solder coupling the electrical probe to the conductive trace. The electrical probe can include a high yield strength wire core including a refractory metal and a thin oxidation protection layer concentrically disposed around high yield strength wire core and providing an outside surface of the electrical probe, the thin oxidation protection layer including predominantly one or more materials selected from gold, platinum, ruthenium, rhodium, palladium, osmium, iridium, chromium, and combinations thereof, wherein the solder fills the cavity and is coupled to the electrical probe inside the cavity, disposed between the electrical probe and the layer.
Abstract translation: 示例包括基板，其包括导电迹线和设置在导电迹线顶部上的层，该层限定延伸到导电迹线的至少一个空腔和设置在该空腔中的电探针，焊料将电探针耦合到 导电痕迹 电探针可以包括高屈服强度的线芯，包括耐火金属和同心地设置在高屈服强度线芯周围的薄氧化保护层，并提供电探针的外表面，薄氧化保护层主要包括一种或多种材料 选自金，铂，钌，铑，钯，锇，铱，铬及其组合，其中焊料填充空腔并且耦合到设置在电探针和层之间的腔内的电探针。
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