公开(公告)号：US09250682B2

公开(公告)日：2016-02-02

申请号：US13732289

申请日：2012-12-31

Applicant: Intel Corporation

Inventor： William C. Hasenplaugh ,  Tryggve Fossum

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3885 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22

Abstract: A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores.

Abstract translation: 用于在包括核心阵列的处理器中执行分布式功率控制的系统和方法使得每个核心能够至少部分地独立地调节功率。 所有核心都可以访问全局电源管理设置，并且内核之间的通信会传播阵列中最近邻居之间的功耗信息。 每个核心都尝试根据全球功耗信息和/或来自全球电源管理员的特定指令来最佳地调节其自身的功耗。 以这种方式，可以以适合于大型核心阵列的可扩展方式来实现本地机会性负载平衡。

公开(公告)号：US20180095728A1

公开(公告)日：2018-04-05

申请号：US15283295

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： William C. Hasenplaugh ,  Kermin E. Fleming, JR. ,  Tryggve Fossum ,  Simon C. Steely, JR.

IPC: G06F7/544 ,  G06F7/487

CPC classification number: G06F7/5443 ,  G06F7/4876

Abstract: A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.

公开(公告)号：US09294419B2

公开(公告)日：2016-03-22

申请号：US13927523

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： William C. Hasenplaugh ,  Tryggve Fossum ,  Judson S. Leonard

IPC: H04L12/933 ,  H04L12/721 ,  H04L12/24 ,  H04L12/733

CPC classification number: H04L49/15 ,  H04L41/12 ,  H04L45/12 ,  H04L45/122 ,  H04L49/101 ,  H04L49/25

Abstract: Architectures, apparatus and systems employing scalable multi-layer 2D-mesh routers. A 2D router mesh comprises bi-direction pairs of linked paths coupled between pairs of IO interfaces and configured in a plurality of rows and columns forming a 2D mesh. Router nodes are located at the intersections of the rows and columns, and are configured to forward data units between IO inputs and outputs coupled to the mesh at its edges through use of shortest path routes defined by agents at the IO interfaces. Multiple instances of the 2D meshes may be employed to support bandwidth scaling of the router architecture. One implementation of a multi-layer 2D mesh is built using a standard tile that is tessellated to form a 2D array of standard tiles, with each 2D mesh layer offset and overlaid relative to the other 2D mesh layers. IO interfaces are then coupled to the multi-layer 2D mesh via muxes/demuxes and/or crossbar interconnects.

Abstract translation: 采用可扩展多层二维网状路由器的架构，设备和系统。 2D路由器网格包括耦合在IO对接口之间的双向对链接路径，并且被配置成形成2D网格的多个行和列。 路由器节点位于行和列的交点处，并且被配置为通过使用由IO接口上的代理定义的最短路径路由来在IO输入和耦合到其边缘的网格的输出之间转发数据单元。 可以采用2D网格的多个实例来支持路由器架构的带宽缩放。 使用被镶嵌的标准瓦片来构建多层2D网格的一个实施方式，以形成标准瓦片的2D阵列，其中每个2D网格层相对于其他2D网格层偏移并重叠。 然后，IO接口通过多路复用/解复用和/或交叉连接互连到多层2D网格。

公开(公告)号：US10402168B2

公开(公告)日：2019-09-03

申请号：US15283295

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： William C. Hasenplaugh ,  Kermin E. Fleming, Jr. ,  Tryggve Fossum ,  Simon C. Steely, Jr.

IPC: G06F7/487 ,  G06F7/544

Abstract: A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.

公开(公告)号：US09317263B2

公开(公告)日：2016-04-19

申请号：US14513402

申请日：2014-10-14

Applicant: Intel Corporation

Inventor： Nicholas Cheng Hwa Chee ,  Tryggve Fossum ,  William C. Hasenplaugh

IPC: G06F9/45 ,  G06F7/38 ,  G06F11/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F11/07

CPC classification number: G06F8/44 ,  G06F9/3001 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/462 ,  G06F11/0751

Abstract: Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.

Abstract translation: 公开了具有故障检测和回滚功能的硬件编译和/或翻译。 编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。 在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令 通过比较第二操作结果与记录的第一操作结果。 在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。

公开(公告)号：US20150046910A1

公开(公告)日：2015-02-12

申请号：US14513402

申请日：2014-10-14

Applicant: Intel Corporation

Inventor： Nicholas Cheng Hwa Chee ,  Tryggve Fossum ,  William C. Hasenplaugh

IPC: G06F9/45 ,  G06F9/38

CPC classification number: G06F8/44 ,  G06F9/3001 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/462 ,  G06F11/0751

Abstract: Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.

Abstract translation: 公开了具有故障检测和回滚功能的硬件编译和/或翻译。 编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。 在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令 通过比较第二操作结果与记录的第一操作结果。 在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。