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公开(公告)号：US20210132123A1
公开(公告)日：2021-05-06
申请号：US17128070
申请日：2020-12-19
Applicant: Intel Corporation
Inventor： Vijay Anand Mathiyalagan , Stephen Gunther
IPC: G01R19/25
Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.
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公开(公告)号：US20220300049A1
公开(公告)日：2022-09-22
申请号：US17203571
申请日：2021-03-16
Applicant: Intel Corporation
Inventor： Somvir Singh Dahiya , Stephen Gunther , Julien Sebot , Randy Osborne , Scot Kellar , Joshua Een
IPC: G06F1/20 , G06F1/3287 , G05B6/02
Abstract: A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.
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Patent Agency Ranking
公开(公告)号：US11269396B2
公开(公告)日：2022-03-08
申请号：US16147285
申请日：2018-09-28
Applicant: Intel Corporation
IPC: G06F1/3234 , G06F1/3296 , G06F1/3228 , G06F1/324
Abstract: An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.
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公开(公告)号：US12242315B2
公开(公告)日：2025-03-04
申请号：US17203571
申请日：2021-03-16
Applicant: Intel Corporation
Inventor： Somvir Singh Dahiya , Stephen Gunther , Julien Sebot , Randy Osborne , Scot Kellar , Joshua Een
IPC: G06F1/32 , G05B6/02 , G06F1/20 , G06F1/3287 , G06F1/3203
Abstract: A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.
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公开(公告)号：US20210208656A1
公开(公告)日：2021-07-08
申请号：US16735563
申请日：2020-01-06
Applicant: Intel Corporation
Inventor： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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公开(公告)号：US12117469B2
公开(公告)日：2024-10-15
申请号：US17128070
申请日：2020-12-19
Applicant: Intel Corporation
Inventor： Vijay Anand Mathiyalagan , Stephen Gunther
CPC classification number: G01R19/2513 , H02J4/00
Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.
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公开(公告)号：US11429172B2
公开(公告)日：2022-08-30
申请号：US16735563
申请日：2020-01-06
Applicant: Intel Corporation
Inventor： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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