公开(公告)号：US20160085443A1

公开(公告)日：2016-03-24

申请号：US14493130

申请日：2014-09-22

Applicant: INTEL CORPORATION

Inventor： SHIGEKI TOMISHIMA ,  SHIH-LIEN L. LU

IPC: G06F3/06 ,  G11C7/10 ,  G11C15/00

CPC classification number: G06F3/061 ,  G06F3/0665 ,  G06F3/0689 ,  G11C7/1006 ,  G11C7/1072 ,  G11C15/00

Abstract: Techniques and mechanisms for determining comparison information at a memory device. In an embodiment, the memory device receives from a memory controller signals that include or otherwise indicate an address corresponding to a memory location of the memory device. Where it is determined that the signals indicate a compare operation, the memory device retrieves data stored at the memory location, and performs a comparison of the data to a reference data value that is included in or otherwise indicated by the received signals. The memory device sends to the memory controller information representing a result of the comparison. In another embodiment, a memory controller provides signals to control a compare operation by such a memory device.

Abstract translation: 用于确定存储设备的比较信息的技术和机制。 在一个实施例中，存储器装置从存储器控制器接收包括或以其他方式指示与存储器件的存储器位置对应的地址的信号。 在确定信号指示比较操作的情况下，存储器件检索存储在存储器位置的数据，并且将数据与参考数据值进行比较，该参考数据值包括在接收到的信号中或以其它方式由接收到的信号指示。 存储器装置向存储器控制器发送表示比较结果的信息。 在另一个实施例中，存储器控制器提供信号以控制这种存储器件的比较操作。

公开(公告)号：US20160379700A1

公开(公告)日：2016-12-29

申请号：US14751801

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： CHARLES AUGUSTINE ,  SHIGEKI TOMISHIMA ,  WEI WU ,  SHIH-LIEN LU ,  JAMES W. TSCHANZ ,  GEORGIOS PANAGOPOULOS ,  HELIA NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路​​，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。

公开(公告)号：US20190043572A1

公开(公告)日：2019-02-07

申请号：US15857340

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： SRIKANTH T. SRINIVASAN ,  SHIGEKI TOMISHIMA

IPC: G11C13/00 ,  G11C11/54 ,  G06N3/063 ,  G06F17/16

CPC classification number: G11C13/0026 ,  G06F17/16 ,  G06G7/16 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0045 ,  H03M1/12

Abstract: Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.