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公开(公告)号:US11482433B2
公开(公告)日:2022-10-25
申请号:US16932594
申请日:2020-07-17
申请人: Intel Corporation
发明人: Ashutosh Sagar , Chao-Kai Liang , Miye Hopkins , Weimin Han , Robert James
IPC分类号: H01L21/67 , H05B6/70 , H01L21/677
摘要: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.
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公开(公告)号:US20220020613A1
公开(公告)日:2022-01-20
申请号:US16932594
申请日:2020-07-17
申请人: Intel Corporation
发明人: Ashutosh Sagar , Chao-Kai Liang , Miye Hopkins , Weimin Han , Robert James
摘要: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.
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公开(公告)号:US20240324167A1
公开(公告)日:2024-09-26
申请号:US18189808
申请日:2023-03-24
申请人: Intel Corporation
发明人: Sudipto Naskar , Abhishek Anil Sharma , Sukru Yemenicioglu , Weimin Han , Van Le
IPC分类号: H10B12/00
CPC分类号: H10B12/00
摘要: A high performance (HP) thin film transistor (TFT) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (BEOL) processes. The HP TFT material is suitable for fabricating the memory stack at the lower BEOL temperatures while still delivering the switching speed requirements of a 3D memory stack in the CIM component. A through silicon via (TSV) architecture connects the logic and the memory in the die.
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公开(公告)号:US11276760B2
公开(公告)日:2022-03-15
申请号:US16435301
申请日:2019-06-07
申请人: Intel Corporation
发明人: Gopinath Bhimarasetti , Walid M. Hafez , Joodong Park , Weimin Han , Raymond E. Cotner , Chia-Hong Jan
IPC分类号: H01L29/36 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L27/088
摘要: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
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公开(公告)号:US10355093B2
公开(公告)日:2019-07-16
申请号:US15122796
申请日:2014-06-26
申请人: Intel Corporation
发明人: Gopinath Bhimarasetti , Walid M. Hafez , Joodong Park , Weimin Han , Raymond E. Cotner , Chia-Hong Jan
IPC分类号: H01L29/36 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L27/088
摘要: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
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公开(公告)号:US20170162693A1
公开(公告)日:2017-06-08
申请号:US15323726
申请日:2014-08-05
申请人: INTEL CORPORATION
发明人: Gopinath Bhimarasetti , Walid Hafez , Joodong Park , Weimin Han , Raymond Cotner
IPC分类号: H01L29/78 , H01L21/762 , H01L29/66 , H01L29/423
CPC分类号: H01L29/7846 , H01L21/02238 , H01L21/02255 , H01L21/76202 , H01L21/823431 , H01L29/42376 , H01L29/66795 , H01L29/785
摘要: Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.
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