Stacked thermal processing chamber modules for remote radiative heating in semiconductor device manufacture

    公开(公告)号:US11482433B2

    公开(公告)日:2022-10-25

    申请号:US16932594

    申请日:2020-07-17

    申请人: Intel Corporation

    IPC分类号: H01L21/67 H05B6/70 H01L21/677

    摘要: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.

    STACKED THERMAL PROCESSING CHAMBER MODULES FOR REMOTE RADIATIVE HEATING IN SEMICONDUCTOR DEVICE MANUFACTURE

    公开(公告)号:US20220020613A1

    公开(公告)日:2022-01-20

    申请号:US16932594

    申请日:2020-07-17

    申请人: Intel Corporation

    IPC分类号: H01L21/67 H05B6/70

    摘要: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.

    Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

    公开(公告)号:US11276760B2

    公开(公告)日:2022-03-15

    申请号:US16435301

    申请日:2019-06-07

    申请人: Intel Corporation

    摘要: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

    Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

    公开(公告)号:US10355093B2

    公开(公告)日:2019-07-16

    申请号:US15122796

    申请日:2014-06-26

    申请人: Intel Corporation

    摘要: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.