公开(公告)号：US20240429276A1

公开(公告)日：2024-12-26

申请号：US18212295

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Shengsi Liu

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. Using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.

公开(公告)号：US20240203869A1

公开(公告)日：2024-06-20

申请号：US18067031

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Nikhil Jasvant Mehta ,  Charles Henry Wallace

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76892 ,  H01L23/53228 ,  H01L23/53257

Abstract: Methods for fabricating an integrated circuit (IC) device with one or more hybrid metal lines are provided. An example IC device includes a substrate; and a metal line extending, along an axis, over the substrate. The metal line has a first end and a second end along the axis. A portion of the metal line at the first end includes a first electrically conductive material. Another portion of the metal line includes a second electrically conductive material, where the second electrically conductive material is different from the first electrically conductive material. In some instances, the first electrically conductive material is a low-resistive, electrically conductive material, and the second electrically conductive material is a direct etch-compatible, electrically conductive material.

公开(公告)号：US20240332285A1

公开(公告)日：2024-10-03

申请号：US18129702

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Abhishek Anil Sharma ,  Sudipto Naskar ,  Kalyan C. Kolluru ,  Chu-Hsin Liang ,  Bashir Uddin Mahmud ,  Van Le

IPC: H01L27/02 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L29/872 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0296 ,  H01L29/6603 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/872 ,  H02H9/046

Abstract: An integrated circuit device comprising a resistor formed on a non-crystalline substrate, the resistor comprising a gate electrode; a gate dielectric in contact with the gate electrode; a source electrode and a drain electrode; and a thin film transistor TFT channel material coupled between the source electrode and the drain electrode.

公开(公告)号：US20240113106A1

公开(公告)日：2024-04-04

申请号：US17957106

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Nikhil J. Mehta ,  Leonard P. Guler ,  Daniel J. Harris

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823481

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. The second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. A second dielectric material is laterally between the first and second sub-fins. A third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. A gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.

公开(公告)号：US20240113104A1

公开(公告)日：2024-04-04

申请号：US17936952

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Tahir Ghani ,  Xinning Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203

Abstract: Techniques are provided to form semiconductor devices that include a gate cut that passes through a plurality of semiconductor bodies (e.g., nanoribbons or nanosheets) such that the gate cut acts as a dielectric spine in a forksheet arrangement with the semiconductor bodies on either side of the gate cut. In an example, two semiconductor devices in a forksheet arrangement include semiconductor bodies directly on either side of a dielectric spine. A gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) that extends around each of the semiconductor bodies of both semiconductor devices. The dielectric spine interrupts the entire height of the gate structure between the two devices and includes dielectric material (e.g., low-k dielectric), and the gate dielectric of the gate structure is not present along sidewalls of the spine between adjacent bodies.

公开(公告)号：US20230275085A1

公开(公告)日：2023-08-31

申请号：US17682037

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Sukru Yemenicioglu ,  Mohit K. Haran ,  Shengsi Liu ,  Robert Joachim ,  Dan S. Lavric ,  Stephen M. Cea

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/41775

Abstract: Techniques are provided herein to form an integrated circuit having a grid of gate cut structures such that a gate cut structure exists between pairs of semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. Each of the gate cut structures may be formed at the same time in a grid-like pattern across the integrated circuit (or a portion thereof). Sidewall spacer structures on the sidewalls of the gate structure wrap around ends of each gate structure to form a given gate cut structure.

公开(公告)号：US20250006812A1

公开(公告)日：2025-01-02

申请号：US18346106

申请日：2023-06-30

Applicant: INTEL CORPORATION

Inventor： Sudipto Naskar ,  Sukru Yemenicioglu ,  Abhishek Anil Sharma ,  Van Le ,  Weimin Han

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

公开(公告)号：US20240332432A1

公开(公告)日：2024-10-03

申请号：US18194303

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Abhishek Anil Sharma ,  Sudipto Naskar ,  Kalyan C. Kolluru

IPC: H01L29/93 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/417 ,  H01L29/66022 ,  H01L29/66196 ,  H01L29/66969 ,  H01L29/2003 ,  H01L29/24

Abstract: An integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (TFT) channel material coupled between the first conductive contact and the second conductive contact.

公开(公告)号：US20240243052A1

公开(公告)日：2024-07-18

申请号：US18622500

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/088 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L27/088 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

公开(公告)号：US20220415795A1

公开(公告)日：2022-12-29

申请号：US17358442

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Mohit Haran ,  Charles Wallace ,  Leanord Guler ,  Sukru Yemenicioglu ,  Mauro Kobrinsky ,  Tahir Ghani

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.