公开(公告)号：US20250006812A1

公开(公告)日：2025-01-02

申请号：US18346106

申请日：2023-06-30

Applicant: INTEL CORPORATION

Inventor： Sudipto Naskar ,  Sukru Yemenicioglu ,  Abhishek Anil Sharma ,  Van Le ,  Weimin Han

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

公开(公告)号：US20240105854A1

公开(公告)日：2024-03-28

申请号：US18528545

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11171243B2

公开(公告)日：2021-11-09

申请号：US16455581

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L29/221 ,  H01L21/8238 ,  H01L27/092

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US10942562B2

公开(公告)日：2021-03-09

申请号：US16146454

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Nageen Himayat ,  Chaitanya Sreerama ,  Hassnaa Moustafa ,  Rita Wouhaybi ,  Linda Hurd ,  Nadine L Dabby ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3212 ,  G06F1/324 ,  G06T15/00 ,  G06K9/00 ,  G06N5/04 ,  G06N20/00 ,  G06F1/3234 ,  G06F1/3206

Abstract: Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.

公开(公告)号：US20190189749A1

公开(公告)日：2019-06-20

申请号：US16326890

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Van Le ,  Seung Hoon Sung ,  Jack Kavalieros ,  Ashish Agrawal ,  Harold Kennel ,  Siddharth Chouksey ,  Anand Murthy ,  Tahir Ghani ,  Glenn Glass ,  Cheng-Ying Huang

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/1079 ,  H01L21/26506 ,  H01L29/16 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66 ,  H01L29/7851

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

公开(公告)号：US20190050049A1

公开(公告)日：2019-02-14

申请号：US16146454

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Nageen Himayat ,  Chaitanya Sreerama ,  Hassnaa Moustafa ,  Rita Wouhaybi ,  Linda Hurd ,  Nadine L Dabby ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: G06F1/32 ,  G06N5/04 ,  G06N99/00 ,  G06K9/00 ,  G06T15/00

Abstract: Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.

公开(公告)号：US12066833B2

公开(公告)日：2024-08-20

申请号：US17322056

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G05D1/00 ,  B60W30/00 ,  G08G1/01 ,  H04W4/029 ,  H04W4/38 ,  H04W4/44

CPC classification number: G05D1/0276 ,  B60W30/00 ,  G05D1/0231 ,  G08G1/0116 ,  H04W4/029 ,  H04W4/38 ,  H04W4/44

Abstract: The present disclosure may be directed to a computer-assisted or autonomous driving (CA/AD) vehicle that receives a plurality of indications of a condition of one or more features of a plurality of locations of a roadway, respectively, encoded in a plurality of navigation signals broadcast by a plurality of transmitters as the CA/AD vehicle drives past the locations enroute to a destination. The CA/AD vehicle may then determine, based in part on the received indications, driving adjustments to be made and send indications of the driving adjustments to a driving control unit of the CA/AD vehicle.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

Abstract: A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US20220122983A1

公开(公告)日：2022-04-21

申请号：US17563983

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Van Le

IPC: H01L27/108 ,  H01L29/786 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  H01L23/528 ,  H01L49/02 ,  H01L29/24 ,  H01L29/66 ,  G11C11/4074

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

公开(公告)号：US11017843B2

公开(公告)日：2021-05-25

申请号：US16457617

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gilbert Dewey ,  Willy Rachmady ,  Van Le ,  Matthew Metz ,  Jack Kavalieros

IPC: G11C11/24 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4094 ,  G11C11/408

Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.