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公开(公告)号：US12265483B2
公开(公告)日：2025-04-01
申请号：US17338479
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Jihwan Kim , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Frank O'Mahony
IPC: G06F13/42 , G06F1/04 , G06F13/16 , H03K17/687 , H03K19/20
Abstract: A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.
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公开(公告)号：US20220200781A1
公开(公告)日：2022-06-23
申请号：US17341150
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Jihwan Kim , Kai Yu , Gurmukh Singh , Stephen Kim , Richard Packard , Frank O'Mahony
Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.
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公开(公告)号：US12184751B2
公开(公告)日：2024-12-31
申请号：US17341150
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Jihwan Kim , Kai Yu , Gurmukh Singh , Stephen Kim , Richard Packard , Frank O'Mahony
Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.
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公开(公告)号：US20220171718A1
公开(公告)日：2022-06-02
申请号：US17338479
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Jihwan Kim , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Frank O'Mahony
IPC: G06F13/16 , H03K19/20 , H03K17/687 , G06F13/42 , G06F1/04
Abstract: A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.
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