公开(公告)号：US12184751B2

公开(公告)日：2024-12-31

申请号：US17341150

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Jihwan Kim ,  Kai Yu ,  Gurmukh Singh ,  Stephen Kim ,  Richard Packard ,  Frank O'Mahony

IPC: H04L7/033 ,  H03K5/135 ,  H03L7/087 ,  H04L7/00

Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

公开(公告)号：US12111786B2

公开(公告)日：2024-10-08

申请号：US17338512

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Jihwan Kim ,  Ajay Balankutty ,  Sandipan Kundu ,  Stephen Kim ,  Frank O'Mahony ,  Kai Yu ,  Bong Chan Kim

IPC: G06F13/42 ,  G06F1/06 ,  G06F1/10 ,  H03K17/687 ,  H03L7/00

CPC classification number: G06F13/4291 ,  G06F1/06 ,  G06F1/10 ,  H03K17/6872 ,  H03K17/6874 ,  H03L7/00

Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.

公开(公告)号：US20220147482A1

公开(公告)日：2022-05-12

申请号：US17338512

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Jihwan Kim ,  Ajay Balankutty ,  Sandipan Kundu ,  Stephen Kim ,  Frank O'Mahony ,  Kai Yu ,  Bong Chan Kim

IPC: G06F13/42 ,  H03K17/687 ,  G06F1/10 ,  G06F1/06

Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.

公开(公告)号：US20220200781A1

公开(公告)日：2022-06-23

申请号：US17341150

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Jihwan Kim ,  Kai Yu ,  Gurmukh Singh ,  Stephen Kim ,  Richard Packard ,  Frank O'Mahony

IPC: H04L7/033 ,  H03K5/135 ,  H04L7/00 ,  H03L7/087

Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.