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公开(公告)号：US20220200781A1
公开(公告)日：2022-06-23
申请号：US17341150
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Jihwan Kim , Kai Yu , Gurmukh Singh , Stephen Kim , Richard Packard , Frank O'Mahony
Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.
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2.发明授权公开(公告)号：US11070200B2
公开(公告)日：2021-07-20
申请号：US16144949
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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公开(公告)号：US09761585B2
公开(公告)日：2017-09-12
申请号：US15425393
申请日：2017-02-06
Applicant: INTEL CORPORATION
Inventor： Sami Hyvonen , Jad B. Rizk , Frank O'Mahony
IPC: H01L27/088 , H01L27/12 , H01L29/423 , H01L29/78 , H01L29/93 , H03L7/099
CPC classification number: H01L27/0886 , H01L27/088 , H01L27/1211 , H01L29/42376 , H01L29/66181 , H01L29/785 , H01L29/93 , H01L29/94 , H03L7/099
Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.
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公开(公告)号：US20170187476A1
公开(公告)日：2017-06-29
申请号：US15457588
申请日：2017-03-13
Applicant: Intel Corporation
Inventor： Tzu-Chien Hsueh , Frank O'Mahony
IPC: H04B17/345
CPC classification number: H04B17/345 , G01R31/2856 , G01R31/31709 , G01R31/31727 , G01R31/31937 , G01R31/40 , H04B15/005
Abstract: Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.
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公开(公告)号：US20160337048A1
公开(公告)日：2016-11-17
申请号：US14710466
申请日：2015-05-12
Applicant: Intel Corporation
Inventor： Tzu-Chien Hsueh , Frank O'Mahony
CPC classification number: H04B17/345 , G01R31/2856 , G01R31/31709 , G01R31/31727 , G01R31/31937 , G01R31/40 , H04B15/005
Abstract: Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.
Abstract translation: 描述了一种装置，其包括：供电分配网络（PDN），用于向至少一个电路提供电力供应; 以及片上同步电源噪声注入器，以向PDN上的电源注入噪声。 描述的另一种装置包括：PDN，用于向各种电路提供电源; 片上电源噪声（PSN）采样器，用注入的噪声对电源进行采样，其中PSN采样器用至少两个不同的时钟信号对电源进行采样; 以及相位噪声累加器，用于随机化所述至少两个不同时钟信号的周期。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20210320652A1
公开(公告)日：2021-10-14
申请号：US17357456
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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公开(公告)号：US09596037B2
公开(公告)日：2017-03-14
申请号：US14710466
申请日：2015-05-12
Applicant: Intel Corporation
Inventor： Tzu-Chien Hsueh , Frank O'Mahony
IPC: H04B15/00 , H04B17/10 , G01R31/317 , G01R31/28
CPC classification number: H04B17/345 , G01R31/2856 , G01R31/31709 , G01R31/31727 , G01R31/31937 , G01R31/40 , H04B15/005
Abstract: Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.
Abstract translation: 描述了一种装置，其包括：供电分配网络（PDN），用于向至少一个电路提供电力供应; 以及片上同步电源噪声注入器，以向PDN上的电源注入噪声。 描述的另一种装置包括：PDN，用于向各种电路提供电源; 片上电源噪声（PSN）采样器，用注入的噪声对电源进行采样，其中PSN采样器用至少两个不同的时钟信号对电源进行采样; 以及相位噪声累加器，用于随机化所述至少两个不同时钟信号的周期。
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8.发明授权公开(公告)号：US12111786B2
公开(公告)日：2024-10-08
申请号：US17338512
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Jihwan Kim , Ajay Balankutty , Sandipan Kundu , Stephen Kim , Frank O'Mahony , Kai Yu , Bong Chan Kim
IPC: G06F13/42 , G06F1/06 , G06F1/10 , H03K17/687 , H03L7/00
CPC classification number: G06F13/4291 , G06F1/06 , G06F1/10 , H03K17/6872 , H03K17/6874 , H03L7/00
Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.
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9.发明授权公开(公告)号：US11722128B2
公开(公告)日：2023-08-08
申请号：US17357456
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
CPC classification number: H03K5/1565 , G06F1/08 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/222 , H03L7/0812
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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10.发明申请公开(公告)号：US20220147482A1
公开(公告)日：2022-05-12
申请号：US17338512
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Jihwan Kim , Ajay Balankutty , Sandipan Kundu , Stephen Kim , Frank O'Mahony , Kai Yu , Bong Chan Kim
IPC: G06F13/42 , H03K17/687 , G06F1/10 , G06F1/06
Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.
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