公开(公告)号：US20230197664A1

公开(公告)日：2023-06-22

申请号：US17558291

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Xavier F. Brun ,  Yuting Wang

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L24/29 ,  H01L25/18 ,  H01L25/0652 ,  H01L25/0655 ,  H01L24/32 ,  H01L23/3675 ,  H01L25/50 ,  H01L24/83 ,  H01L24/96 ,  H01L21/568 ,  H01L21/561 ,  H01L2224/83132 ,  H01L2224/8389 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/29188 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/05994 ,  H01L2224/83193 ,  H01L24/27 ,  H01L23/3736

Abstract: A semiconductor package includes a semiconductor subassembly disposed on a package substrate and including: a first layer including first dies, and an encapsulation material encapsulating the first dies; a second layer adjacent the first layer and including a substrate; a solid component disposed on the first layer; and an interface layer disposed between and mechanically bonding the solid component and the first layer. The interface layer provides a direct dielectric-to-dielectric bond including a first dielectric sublayer directly adjacent the first layer, and a second dielectric sublayer directly adjacent the first dielectric sublayer and including an amorphous material. Second dies may be disposed on the package substrate adjacent the semiconductor subassembly. A heat spreader is disposed over the semiconductor subassembly and the second dies; and a TIM is coupled to the heat spreader at one side thereof, and to respective ones of the semiconductor subassembly and the one or more dies at another side thereof.

公开(公告)号：US20230088170A1

公开(公告)日：2023-03-23

申请号：US17481068

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Xavier Francois Brun ,  Sanka Ganesan ,  Holly Sawyer ,  William J. Lambert ,  Timothy A. Gosselin ,  Yuting Wang

IPC: H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

公开(公告)号：US20250118698A1

公开(公告)日：2025-04-10

申请号：US18987884

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Xavier Francois Brun ,  Sanka Ganesan ,  Holly Sawyer ,  William J. Lambert ,  Timothy A. Gosselin ,  Yuting Wang

IPC: H01L25/11 ,  H01L23/00 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.