公开(公告)号：US20240363465A1

公开(公告)日：2024-10-31

申请号：US18309546

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Daiki Komatsu ,  Hau Nguyen

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/78 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L21/568 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/05558 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/05442 ,  H01L2924/0695 ,  H01L2924/07025

Abstract: An electronic device includes a semiconductor die, a die attach pad, an adhesive, a conductive lead, and a package structure, where the semiconductor die has opposite first and second sides, a conductive terminal on the second side, and an electrical isolation coating layer that extends on the first side, the adhesive adheres the first side of the semiconductor die to the die attach pad, the conductive lead is electrically coupled to the conductive terminal of the semiconductor die, and the package structure encloses at least a portion of the semiconductor die.

公开(公告)号：US20240332261A1

公开(公告)日：2024-10-03

申请号：US18733880

申请日：2024-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Jung Yang ,  Hsien-Wei Chen

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/03 ,  H01L2224/02373 ,  H01L2224/03616 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/0812 ,  H01L2224/18 ,  H01L2224/273 ,  H01L2224/27614 ,  H01L2224/27616 ,  H01L2224/29016 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/19011 ,  H01L2924/19102

Abstract: A method of manufacturing a die stack structure includes the following steps. A first bonding structure is formed over a front side of a first die. The method of forming the first bonding structure includes the following steps. A first bonding dielectric material is formed on a first test pad of the first die. A first blocking layer is formed over the first bonding dielectric material. A second bonding dielectric material and a first dummy metal layer are formed over the first blocking layer. The first dummy metal layer and the first test pad are electrically isolated from each other by the first blocking layer. Thereafter, a second bonding structure is formed over a front side of a second die. The first die and the second die are bonded through the first bonding structure and the second bonding structure.

公开(公告)号：US20240313025A1

公开(公告)日：2024-09-19

申请号：US18603032

申请日：2024-03-12

Applicant: CANON KABUSHIKI KAISHA

Inventor： RYO YOSHIDA ,  HIROSHI IKAKURA ,  SHO SUZUKI ,  KENJI TOGO

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/08 ,  H01L24/80 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05042 ,  H01L2924/05442

Abstract: In a stack type photoelectric conversion apparatus in which a first substrate and a second substrate are bonded with junction electrodes disposed on the respective substrates, a first silicon nitride film disposed on the first substrate and a second silicon nitride film disposed on the second substrate differ in compression stress.

公开(公告)号：US20240312820A1

公开(公告)日：2024-09-19

申请号：US18595341

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Yoshio MIZUTA

IPC: H01L21/68 ,  G03F7/00 ,  H01L21/66 ,  H01L21/67 ,  H01L23/00 ,  H01L21/311 ,  H01L21/683

CPC classification number: H01L21/68 ,  G03F7/70775 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/20 ,  H01L24/80 ,  H01L21/31105 ,  H01L21/6838 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80123 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/05042 ,  H01L2924/05442

Abstract: According to embodiments, a semiconductor manufacturing apparatus includes a control circuit configured to acquire, for a pair of substrates including a first substrate and a second substrate, a warp amount of the first substrate, the warp amount of the first substrate including an amount of protrusion of a portion of the first substrate relative to an edge of the first substrate; determine a desired size for a gap between the first and second substrates based on the acquired warp amount; and control a chuck movement device to move one of the first and second substrates to adjust the gap to the determined size before the first and second substrates are bonded.

公开(公告)号：US12014999B2

公开(公告)日：2024-06-18

申请号：US17031587

申请日：2020-09-24

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Bahareh Sadeghimakki

IPC: H01G11/36 ,  H01L23/00 ,  H01L33/62 ,  H03H3/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/03614 ,  H01L2224/0363 ,  H01L2224/03632 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/056 ,  H01L2224/08225 ,  H01L2224/27614 ,  H01L2224/27632 ,  H01L2224/29005 ,  H01L2224/29019 ,  H01L2224/29078 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29355 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/29439 ,  H01L2224/29499 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29639 ,  H01L2224/32227 ,  H01L2224/80805 ,  H01L2224/80897 ,  H01L2224/83193 ,  H01L2224/83897 ,  H03H3/00 ,  H01L2224/29139 ,  H01L2924/00014 ,  H01L2224/29609 ,  H01L2924/00014 ,  H01L2224/29611 ,  H01L2924/00014 ,  H01L2224/29639 ,  H01L2924/00014 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29355 ,  H01L2924/00014 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2224/29439 ,  H01L2924/00014

Abstract: This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

公开(公告)号：US20240178167A1

公开(公告)日：2024-05-30

申请号：US18437444

申请日：2024-02-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ran He ,  Huifang Jiao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03845 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05584 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/80357 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059

Abstract: The invention provide a chip package structure, which includes a first chip and a first hybrid bonding structure. The first chip is connected to another chip through the first hybrid bonding structure. The first hybrid bonding structure includes a first bonding layer. The first bonding layer is disposed on a side away from a substrate of the first chip, and the first bonding layer includes a first insulation material and a plurality of first metal solder pads embedded in the first insulation material. Each of the plurality of first metal solder pads includes a groove structure. A groove bottom of the groove structure is buried in the first insulation material, and a groove opening of the groove structure is exposed to a surface of the first insulation material and is flush with the surface of the first insulation material.

公开(公告)号：US11929335B2

公开(公告)日：2024-03-12

申请号：US17382325

申请日：2021-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05016 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/351

Abstract: A semiconductor structure for wafer level bonding includes a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface, and a sidewall between the top surface and the bottom surface. A bottom angle between the bottom surface and sidewall of the bonding pad is smaller than 90 degrees.

公开(公告)号：US20240047446A1

公开(公告)日：2024-02-08

申请号：US17882626

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Yen Chang ,  Chun-Cheng Lin ,  Chih-Wei Lin ,  Yi-Da Tsai ,  Hsaing-Pin Kuan ,  Chih-Chiang Tsao ,  Hsuan-Ting Kuo ,  Hsiu-Jen Lin ,  Yu-Chia Lai ,  Kuo-Lung Pan ,  Hao-Yi Tsai ,  Ching-Hua Hsieh

IPC: H01L25/18 ,  H01L23/00 ,  H01R12/57 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/19 ,  H01L24/95 ,  H01R12/57 ,  H01L24/13 ,  H01L25/0652 ,  H01L24/20 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L24/11 ,  H01L2224/19 ,  H01L2224/95001 ,  H01L2224/214 ,  H01L2224/2101 ,  H01L2224/81815 ,  H01L2224/81201 ,  H01L2224/81862 ,  H01L2224/81193 ,  H01L2224/81906 ,  H01L2224/1403 ,  H01L2224/14517 ,  H01L2224/14505 ,  H01L2224/1319 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/07025 ,  H01L2224/1329 ,  H01L2224/13386 ,  H01L2924/05442 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13144 ,  H01L2224/16108 ,  H01L2224/16238 ,  H01L2224/16059 ,  H01L2224/13016 ,  H01L2224/1607 ,  H01L2224/8192 ,  H01L2224/1131 ,  H01L2924/1427 ,  H01L2924/14361 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1431

Abstract: A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

公开(公告)号：US20230420411A1

公开(公告)日：2023-12-28

申请号：US17846153

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L25/18 ,  H01L24/06 ,  H01L25/50 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05567 ,  H01L2224/06102 ,  H01L2224/06183 ,  H01L2224/08146 ,  H01L2224/08137 ,  H01L2224/0557 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/80006

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

公开(公告)号：US11776923B2

公开(公告)日：2023-10-03

申请号：US17180359

申请日：2021-02-19

Applicant: SONY CORPORATION

Inventor： Masaki Haneda

IPC: H01L21/768 ,  H01L23/00 ,  H01L27/14 ,  H01L25/065 ,  H01L27/146 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L27/14 ,  H01L27/1469 ,  H01L27/14634 ,  H01L27/14636 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05007 ,  H01L2224/0566 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0801 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80009 ,  H01L2224/80097 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/0104 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/05442 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/00014 ,  H01L2224/0566 ,  H01L2924/00014 ,  H01L2224/05618 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/80986 ,  H01L2224/80896 ,  H01L2224/8082

Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.