公开(公告)号：US20190304808A1

公开(公告)日：2019-10-03

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Edvin CETEGEN ,  Yuying WEI ,  Sushrutha GUJJULA ,  Nisha ANANTHAKRISHNAN ,  Shan ZHONG

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

公开(公告)号：US20220165585A1

公开(公告)日：2022-05-26

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Edvin CETEGEN ,  Yuying WEI ,  Sushrutha GUJJULA ,  Nisha ANANTHAKRISHNAN ,  Shan ZHONG

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

公开(公告)号：US20200006169A1

公开(公告)日：2020-01-02

申请号：US16022528

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： William WARREN ,  Taylor GAINES ,  Frederick ATADANA ,  Edvin CETEGEN ,  Vipul MEHTA ,  Hsin-Yu LI ,  Yuying WEI ,  Yang GUO ,  Ren ZHANG

IPC: H01L23/16 ,  H01L23/31

Abstract: A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.