公开(公告)号：US20210305132A1

公开(公告)日：2021-09-30

申请号：US16828405

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Digvijay RAORANE ,  Sairam AGRAHARAM ,  Nitin DESHPANDE ,  Mitul MODI ,  Manish DUBEY ,  Edvin CETEGEN

IPC: H01L23/482 ,  H01L23/538 ,  H01L23/495

Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

公开(公告)号：US20200043894A1

公开(公告)日：2020-02-06

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George VAKANAS ,  Aastha UPPAL ,  Shereen ELHALAWATY ,  Aaron MCCANN ,  Edvin CETEGEN ,  Tannaz HARIRCHIAN ,  Saikumar JAYARAMAN

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US20240213074A1

公开(公告)日：2024-06-27

申请号：US18089468

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Mark SALTAS ,  Edvin CETEGEN ,  Tony DAMBRAUSKAS ,  Albert KAMGA ,  Mine KAYA ,  James MELLODY ,  Rajesh Kumar NEERUKATTI

IPC: H01L21/683 ,  B25J15/06

CPC classification number: H01L21/6838 ,  B25J15/0616 ,  H01L2224/81203

Abstract: This disclosure describes nozzle designs for holding disaggregated die flat in a bonding process. The nozzle designs may have trenches extending radially outward from the center of the nozzle to the corners, such as in a snowflake pattern. The trenches may be positioned to be axially unaligned with any mold dishes of the disaggregated die when lifting the disaggregated die. The trenches may have a depth of at least 200 micrometers to allow for sufficient air flow to prevent warpage of the disaggregated die.

公开(公告)号：US20210242107A1

公开(公告)日：2021-08-05

申请号：US16781563

申请日：2020-02-04

Applicant: Intel Corporation

Inventor： Wei LI ,  Edvin CETEGEN ,  Nicholas S. HAEHN ,  Mitul MODI ,  Nicholas NEAL

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

公开(公告)号：US20200098661A1

公开(公告)日：2020-03-26

申请号：US16139401

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Kelly LOFGREEN ,  Chia-Pin CHIU ,  Joseph PETRINI ,  Edvin CETEGEN ,  Betsegaw GEBREHIWOT ,  Feras EID

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

公开(公告)号：US20230343723A1

公开(公告)日：2023-10-26

申请号：US18216005

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L23/5381 ,  H01L23/3675

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

公开(公告)号：US20230238355A1

公开(公告)日：2023-07-27

申请号：US18127539

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Wei LI ,  Edvin CETEGEN ,  Nicholas S. HAEHN ,  Ram S. VISWANATH ,  Nicholas NEAL ,  Mitul MODI

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/78 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US20230086649A1

公开(公告)日：2023-03-23

申请号：US17483621

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Onur OZKAN ,  Edvin CETEGEN ,  Steve CHO ,  Nicholas S. HAEHN ,  Jacob VEHONSKY

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

Abstract: An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.

公开(公告)号：US20210035921A1

公开(公告)日：2021-02-04

申请号：US16526087

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

公开(公告)号：US20190148268A1

公开(公告)日：2019-05-16

申请号：US16228378

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Rajendra C. DIAS ,  Edvin CETEGEN ,  Lars D. SKOGLUND

IPC: H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.