公开(公告)号：US20210035859A1

公开(公告)日：2021-02-04

申请号：US16526012

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Vipul MEHTA ,  Yiqun BAI ,  Ziyin LIN ,  John DECKER ,  Yan LI

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.

公开(公告)号：US20220196937A1

公开(公告)日：2022-06-23

申请号：US17132851

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bassam ZIADEH ,  Jingyi HUANG ,  Yiqun BAI ,  Ziyin LIN ,  Vipul MEHTA ,  Joseph VAN NAUSDLE

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

公开(公告)号：US20240153837A1

公开(公告)日：2024-05-09

申请号：US17983226

申请日：2022-11-08

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Jonas CROISSANT ,  Jigneshkumar PATEL ,  Dingying XU ,  Gang DUAN ,  Aditya Sumanth YERRAMILLI ,  Suriyakala RAMALINGAM ,  Xavier BRUN

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L23/3157 ,  H01L23/49811 ,  H01L25/18 ,  H01L24/32 ,  H01L2224/32225

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.

公开(公告)号：US20240402445A1

公开(公告)日：2024-12-05

申请号：US18798574

申请日：2024-08-08

Applicant: Intel Corporation

Inventor： Bassam ZIADEH ,  Jingyi HUANG ,  Yiqun BAI ,  Ziyin LIN ,  Vipul MEHTA ,  Joseph VAN NAUSDLE

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

公开(公告)号：US20210066162A1

公开(公告)日：2021-03-04

申请号：US16557896

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Sergio A. CHAN ARGUEDAS ,  Nicholas S. HAEHN ,  Edvin CETEGEN ,  Nicholas NEAL ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON ,  Vipul MEHTA

IPC: H01L23/42 ,  H01L23/00

Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.

公开(公告)号：US20210020531A1

公开(公告)日：2021-01-21

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20190304808A1

公开(公告)日：2019-10-03

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Edvin CETEGEN ,  Yuying WEI ,  Sushrutha GUJJULA ,  Nisha ANANTHAKRISHNAN ,  Shan ZHONG

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

公开(公告)号：US20240258183A1

公开(公告)日：2024-08-01

申请号：US18632047

申请日：2024-04-10

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20220165585A1

公开(公告)日：2022-05-26

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Edvin CETEGEN ,  Yuying WEI ,  Sushrutha GUJJULA ,  Nisha ANANTHAKRISHNAN ,  Shan ZHONG

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

公开(公告)号：US20210066152A1

公开(公告)日：2021-03-04

申请号：US16557891

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Elizabeth NOFEN ,  Vipul MEHTA ,  Taylor GAINES

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/67 ,  H01L23/373 ,  H01L23/367

Abstract: A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material