公开(公告)号：US20190067163A1

公开(公告)日：2019-02-28

申请号：US16102117

申请日：2018-08-13

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna ,  Eytan Mann ,  Sidharth Dalmia

IPC: H01L23/433 ,  H01L23/367 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L21/4814 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/38 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

公开(公告)号：US10103088B1

公开(公告)日：2018-10-16

申请号：US15473251

申请日：2017-03-29

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Brian R. Butcher ,  Carlton E. Hanna ,  Hong Wei Hu

IPC: H01L23/498 ,  H01L23/433 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.

公开(公告)号：US20180286815A1

公开(公告)日：2018-10-04

申请号：US15474251

申请日：2017-03-30

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna

IPC: H01L23/552 ,  H01L23/60 ,  H01L23/498 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/285

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a shielding structure disposed on a surface of a package structure, wherein the shielding structure comprises a film; a conductive material disposed on a surface of the film; and a plurality of conductive bars, wherein each individual conductive bar of the plurality of conductive bars is disposed through the film, and at least a portion of the plurality of conductive bars is physically coupled with grounding traces disposed on the surface of the package structure.

公开(公告)号：US10332821B2

公开(公告)日：2019-06-25

申请号：US16102117

申请日：2018-08-13

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna ,  Eytan Mann ,  Sidharth Dalmia

IPC: H01L23/498 ,  H01L23/433 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

公开(公告)号：US20180286780A1

公开(公告)日：2018-10-04

申请号：US15473251

申请日：2017-03-29

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Brian R. Butcher ,  Carlton E. Hanna ,  Hong Wei Hu

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.

公开(公告)号：US10049961B1

公开(公告)日：2018-08-14

申请号：US15474301

申请日：2017-03-30

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna ,  Eytan Mann ,  Sidharth Dalmia

IPC: H01L23/498 ,  H01L23/433 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/367

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.