公开(公告)号：US10332821B2

公开(公告)日：2019-06-25

申请号：US16102117

申请日：2018-08-13

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna ,  Eytan Mann ,  Sidharth Dalmia

IPC: H01L23/498 ,  H01L23/433 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

公开(公告)号：US10049961B1

公开(公告)日：2018-08-14

申请号：US15474301

申请日：2017-03-30

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna ,  Eytan Mann ,  Sidharth Dalmia

IPC: H01L23/498 ,  H01L23/433 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/367

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

公开(公告)号：US20190067163A1

公开(公告)日：2019-02-28

申请号：US16102117

申请日：2018-08-13

Applicant: Intel IP Corporation

Inventor： Quan Qi ,  Carlton E. Hanna ,  Eytan Mann ,  Sidharth Dalmia

IPC: H01L23/433 ,  H01L23/367 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L21/4814 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/38 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

公开(公告)号：US10164732B2

公开(公告)日：2018-12-25

申请号：US14748293

申请日：2015-06-24

Applicant: Intel IP Corporation

Inventor： Christoph Schultz ,  William Dawson Kesling ,  Eytan Mann

IPC: H04L25/03 ,  H04L1/00 ,  H04L25/02 ,  H04L25/49 ,  H04B1/04 ,  H03K19/003 ,  H04B3/32 ,  H04L25/08

Abstract: An encoding circuit for selecting a transmit data symbol for transmission over a data bus may include an alternate symbol generation circuit configured to generate an alternate data symbol based on an encoded data symbol scheduled for transmission over the data bus and a decision circuit configured to select the encoded data symbol or the alternate data symbol as the transmit symbol based on a plurality of phasors. The decision circuit may include a plurality of phasor generation circuits configured to generate the plurality of phasors based on the encoded data symbol and a plurality of target frequencies.

公开(公告)号：US20180011813A1

公开(公告)日：2018-01-11

申请号：US15202910

申请日：2016-07-06

Applicant: INTEL IP CORPORATION

Inventor： Eytan Mann ,  Gilad Nahor ,  Guy Kaminitz

IPC: G06F13/42 ,  G06F1/10 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F1/10 ,  G06F1/3287 ,  G06F13/4022

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for a serial mid-speed interface. A first component includes a phase-locked loop (PLL) to receive an input clock signal and to output an output signal, an interface controller including a clock-management state machine, and a transmitter. The interface controller is to receive the input clock signal, receive the output signal from the PLL, and generate a speed-switch packet. The transmitter is to transmit a first plurality of packets to a second component at a clock rate based on the clock signal via a mid-speed interface, transmit the speed-switch packet to the second component, and transmit a second plurality of packets to the second component at a PLL rate based on the output signal, where the PLL rate is greater than the clock rate.

公开(公告)号：US20160380721A1

公开(公告)日：2016-12-29

申请号：US14748293

申请日：2015-06-24

Applicant: Intel IP Corporation

Inventor： Christoph Schultz ,  William Dawson Kesling ,  Eytan Mann

IPC: H04L1/00

CPC classification number: H04L1/0011 ,  H03K19/00346 ,  H04B1/0475 ,  H04B3/32 ,  H04L1/0033 ,  H04L25/0276 ,  H04L25/08 ,  H04L25/49

Abstract: An encoding circuit for selecting a transmit data symbol for transmission over a data bus may include an alternate symbol generation circuit configured to generate an alternate data symbol based on an encoded data symbol scheduled for transmission over the data bus and a decision circuit configured to select the encoded data symbol or the alternate data symbol as the transmit symbol based on a plurality of phasors. The decision circuit may include a plurality of phasor generation circuits configured to generate the plurality of phasors based on the encoded data symbol and a plurality of target frequencies.

Abstract translation: 用于选择用于通过数据总线传输的发送数据符号的编码电路可以包括：替代符号生成电路，被配置为基于被调度用于通过数据总线传输的编码数据符号生成替代数据符号;以及判定电路， 编码数据符号或替代数据符号作为基于多个相量的发送符号。 判定电路可以包括多个相量生成电路，其被配置为基于编码数据符号和多个目标频率来生成多个相量。