-
公开(公告)号：US09536780B1
公开(公告)日：2017-01-03
申请号：US15130814
申请日：2016-04-15
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76834 , C23C16/45544 , C23C16/50 , H01L21/3212 , H01L21/67098 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/7684 , H01L21/76841 , H01L21/76843 , H01L21/76861 , H01L21/76883 , H01L21/76885 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L27/1087
摘要： The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.
摘要翻译： 本公开涉及使用单个室进行多次处理，导致具有互连的半导体芯片。 许多示例性方法包括形成通孔以暴露微芯片的多个层。 这些层可以包括图案化介电层，封盖层，第一金属层和绝缘体。 然后实施表面改性步骤以修饰和/或致密化电介质表面的经处理的表面。 然后执行金属化合物去除步骤以从通孔的底部除去金属化合物。 最后，通孔填充导电材料。 表面改性和金属化合物去除步骤在一个室中实现。
-
公开(公告)号：US09824917B2
公开(公告)日：2017-11-21
申请号：US15496172
申请日：2017-04-25
IPC分类号： H01L21/768 , H01L21/321 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76834 , C23C16/45544 , C23C16/50 , H01L21/3212 , H01L21/67098 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/7684 , H01L21/76841 , H01L21/76843 , H01L21/76861 , H01L21/76883 , H01L21/76885 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L27/1087
摘要： The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.
-
公开(公告)号：US09702042B1
公开(公告)日：2017-07-11
申请号：US15352917
申请日：2016-11-16
IPC分类号： H01L21/768 , C23C16/455 , C23C16/50 , H01L27/108 , H01L21/67
CPC分类号： H01L21/76834 , C23C16/45544 , C23C16/50 , H01L21/3212 , H01L21/67098 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/7684 , H01L21/76841 , H01L21/76843 , H01L21/76861 , H01L21/76883 , H01L21/76885 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L27/1087
摘要： The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.
-
-
搜索结果
3 条记录 (耗时 0.013 秒)
