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公开(公告)号：US10660209B2
公开(公告)日：2020-05-19
申请号：US15811852
申请日：2017-11-14
摘要： A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.
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公开(公告)号：US20190150287A1
公开(公告)日：2019-05-16
申请号：US15811852
申请日：2017-11-14
摘要： A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.
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公开(公告)号：US20200245466A1
公开(公告)日：2020-07-30
申请号：US16851424
申请日：2020-04-17
摘要： A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.
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公开(公告)号：US11388821B2
公开(公告)日：2022-07-12
申请号：US16851424
申请日：2020-04-17
摘要： A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.
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公开(公告)号：US20200075468A1
公开(公告)日：2020-03-05
申请号：US16120782
申请日：2018-09-04
IPC分类号： H01L23/498 , H01L25/16 , H01L49/02
摘要： An integrated circuit (IC) chip carrier includes one or more internal metal planes. A dedicated metal plane (DMP) may be formed upon a metal plane dielectric layer. The metal plane dielectric layer may be formed upon a first dielectric layer that is formed upon an IC chip carrier core. The DMP may be formed of the same or different material relative to the material of the wires of the IC chip carrier. The side surfaces of the DMP may be coplanar with associated side surfaces of the IC chip carrier. The DMP may transfer heat from the IC chip horizontally to its side surfaces. A decoupling capacitor is externally connected to the IC chip carrier and is electrically connected to the DMP. By connecting the decoupling capacitor to the DMP, the decoupling capacitor may further reduce inductance and noise within the IC chip system.
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公开(公告)号：US10423752B2
公开(公告)日：2019-09-24
申请号：US15719743
申请日：2017-09-29
发明人： Anson J. Call , Francesco Preda , Paul R. Walling
IPC分类号： G06F17/50
摘要： Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
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7.发明授权Fabrication method for circuit substrate having post-fed die side power supply connections 失效具有后馈模头侧电源连接的电路基板的制造方法公开(公告)号：US08722536B2
公开(公告)日：2014-05-13
申请号：US13959003
申请日：2013-08-05
IPC分类号： H01L21/44
CPC分类号： H01L21/768 , H01L23/49827 , H01L23/50 , H01L24/16 , H01L2224/16 , H01L2924/01078 , H01L2924/14 , H01L2924/19041 , H01L2924/19105 , H05K1/0231 , H05K1/0263 , H05K1/113 , H05K3/429 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718 , H05K2201/10674 , Y10T29/49165
摘要： A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.
摘要翻译： 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。
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8.发明申请FABRICATION METHOD FOR CIRCUIT SUBSTRATE HAVING POST-FED DIE SIDE POWER SUPPLY CONNECTIONS 失效具有后置电源电源连接的电路基板的制造方法公开(公告)号：US20130316534A1
公开(公告)日：2013-11-28
申请号：US13959003
申请日：2013-08-05
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L23/49827 , H01L23/50 , H01L24/16 , H01L2224/16 , H01L2924/01078 , H01L2924/14 , H01L2924/19041 , H01L2924/19105 , H05K1/0231 , H05K1/0263 , H05K1/113 , H05K3/429 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718 , H05K2201/10674 , Y10T29/49165
摘要： A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.
摘要翻译： 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。
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公开(公告)号：US10956649B2
公开(公告)日：2021-03-23
申请号：US16547623
申请日：2019-08-22
发明人： Anson J. Call , Francesco Preda , Paul R. Walling
IPC分类号： G06F30/398 , G06F30/394 , G06F111/10 , G06F113/18 , G06F113/20
摘要： Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
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公开(公告)号：US20190102506A1
公开(公告)日：2019-04-04
申请号：US15719743
申请日：2017-09-29
发明人： Anson J. Call , Francesco Preda , Paul R. Walling
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/16 , G06F2217/38 , G06F2217/40
摘要： Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
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