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公开(公告)号：US20190123100A1
公开(公告)日：2019-04-25
申请号：US16227065
申请日：2018-12-20
Applicant: International Business Machines Corporation
Inventor： ROBERT BRUCE , Fabio Carta , Gloria WingYun Fraczak , Hiroyuki Miyazoe , Kumar R. Virwani
Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
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公开(公告)号：US20170047515A1
公开(公告)日：2017-02-16
申请号：US15343602
申请日：2016-11-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Mohit Bajaj , Arpan K. Deb , Aniruddha Konar , Kota V. R. M. Murali , Rajan K. Pandey , Kumar R. Virwani
CPC classification number: H01L45/1666 , B82Y10/00 , H01L21/02568 , H01L21/0262 , H01L27/224 , H01L27/2409 , H01L29/157 , H01L29/24 , H01L29/66121 , H01L29/8618 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/16 , H01L45/1608 , H01L45/165 , Y10S977/76 , Y10S977/943
Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
Abstract translation: 本发明一般涉及高电流密度访问装置（AD），更具体地说，涉及使用含铜混合离子电子传导层的相变存储器（PCM）块中形成可调电压余量存取二极管的结构和方法 （MIEC）材料。 本发明的实施例可以使用层MIEC材料来形成可以提供高电流密度并且在与标准BEOL处理兼容的温度下制造时可靠地操作的接入装置。 通过改变沉积技术和使用的MIEC材料的量，可将接入设备的电压余量（即，器件导通的电压和电流高于本底噪声）调谐到不同存储器件的特定操作条件。
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公开(公告)号：US12284922B2
公开(公告)日：2025-04-22
申请号：US17679418
申请日：2022-02-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Hiroyuki Miyazoe , Gloria W. Y. Fraczak , Kumar R. Virwani , Takashi Ando
Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.
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公开(公告)号：US20200287135A1
公开(公告)日：2020-09-10
申请号：US16291177
申请日：2019-03-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Hiroyuki Miyazoe , Gloria W.Y. Fraczak , Kumar R. Virwani , Takashi Ando
Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.
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公开(公告)号：US20190115392A1
公开(公告)日：2019-04-18
申请号：US15784343
申请日：2017-10-16
Applicant: International Business Machines Corporation
Inventor： ROBERT BRUCE , Fabio Carta , Gloria WingYun Fraczak , Hiroyuki Miyazoe , Kumar R. Virwani
Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09766170B2
公开(公告)日：2017-09-19
申请号：US14607291
申请日：2015-01-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Geraud J. Dubois , Jane E. Frommer , Robin S. King , Krystelle Lionti , Kumar R. Virwani , Willi Volksen
IPC: G01N3/42
CPC classification number: G01N3/42 , G01N2203/0218 , G01N2203/0286
Abstract: A method and computer product program for determining Young's modulus. The method includes placing a probe in contact with a surface of a material on a substrate and, with an initial force of 800 nano newtons or less; determining the location of the surface relative to an initial indentation depth for the initial force; increasing the force on the probe from the initial force to a maximum force greater than the initial force to generate a load curve; decreasing the force on the probe from the maximum force to the initial force to generate an unload curve, the maximum force selected such that the unload curve is independent of the presence of the substrate; and using the unload curve, determining a relationship between (i) the reduced modulus of the sample material and (ii) the ratio of probe penetration depth and the thickness of the layer.
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公开(公告)号：US09508930B2
公开(公告)日：2016-11-29
申请号：US15132675
申请日：2016-04-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Mohit Bajaj , Arpan K. Deb , Aniruddha Konar , Kota V. R. M. Murali , Rajan K. Pandey , Kumar R. Virwani
IPC: H01L21/28 , H01L21/44 , H01L29/40 , H01L33/02 , H01L45/00 , H01L29/861 , H01L29/66 , H01L29/15 , H01L29/24
CPC classification number: H01L45/1666 , B82Y10/00 , H01L21/02568 , H01L21/0262 , H01L27/224 , H01L27/2409 , H01L29/157 , H01L29/24 , H01L29/66121 , H01L29/8618 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/16 , H01L45/1608 , H01L45/165 , Y10S977/76 , Y10S977/943
Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
Abstract translation: 本发明一般涉及高电流密度访问装置（AD），更具体地说，涉及使用含铜混合离子电子传导层的相变存储器（PCM）块中形成可调电压余量存取二极管的结构和方法 （MIEC）材料。 本发明的实施例可以使用层MIEC材料来形成可以提供高电流密度并且在与标准BEOL处理兼容的温度下制造时可靠地操作的接入装置。 通过改变沉积技术和使用的MIEC材料的量，可将接入设备的电压余量（即器件导通的电压和电流高于本底噪声）调谐到不同存储器件的特定操作条件。
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公开(公告)号：US20160083520A1
公开(公告)日：2016-03-24
申请号：US14958992
申请日：2015-12-04
Applicant: International Business Machines Corporation
Inventor： James L. Hedrick , Jeannette M. O'Brien , Kumar R. Virwani
IPC: C08G73/06 , C09D179/04
CPC classification number: C08G73/0644 , C08G65/00 , C08G65/333 , C08G65/33303 , C08G65/33306 , C08G65/33313 , C08G65/33396 , C08G73/06 , C08G73/065 , C09D171/00 , C09D171/02 , C09D179/04
Abstract: Polyhexahydrotriazine (PHT) film layers are formed by a process comprising heating a first mixture comprising i) a solvent, ii) paraformaldehyde, and iii) a diamine monomer comprising two primary aromatic amine groups at a temperature of about 20° C. to less than 150° C. This heating step forms a stable polyhemiaminal (PHA) in solution, which can be cast on a surface of a substrate, thereby forming an initial film layer comprising the PHA. The initial film layer is heated at a temperature of 180° C. to about 280° C., thereby converting the PHA film layer to a PHT film layer. Young's moduli of about 8 GPA to about 14 GPA have been observed for the PHT film layers.
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公开(公告)号：US11273357B2
公开(公告)日：2022-03-15
申请号：US16117045
申请日：2018-08-30
Applicant: International Business Machines Corporation
Inventor： Pawan Chowdhary , Kumar R. Virwani , Charles Thomas Rettner , Bulent N. Kurdi
Abstract: Embodiments relate to a system, program product, and method for use and an artificial intelligence (AI) platform to identify and analyze physical forces related to sensory input. A sensor operatively coupled to an inertial measurement unit (IMU) is activated. An initial position of the IMU responsive to the sensor activation is captured and movement of the IMU from the initial position is recognized. A comparison is preformed, where the captured initial position is compared to a second position which is correlated with the recognized movement. A score based on the performed comparison is determined and a diagnostic assessment based on the performed comparison and determined score is created. The diagnostic assessment is converted to feedback, where the conversion utilizes real-time communication of an instruction of a second movement position of the IMU. Receipt of the feedback physically conveys a manifestation of the feedback to the apparatus.
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公开(公告)号：US10903270B2
公开(公告)日：2021-01-26
申请号：US16227091
申请日：2018-12-20
Applicant: International Business Machines Corporation
Inventor： Robert Bruce , Fabio Carta , Gloria WingYun Fraczak , Hiroyuki Miyazoe , Kumar R. Virwani
Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
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