公开(公告)号：US12219737B2

公开(公告)日：2025-02-04

申请号：US16445470

申请日：2019-06-19

Applicant: International Business Machines Corporation

Inventor： Oblesh Jinka ,  Salvatore Bernardo Olivadese ,  Sean Hart ,  Nicholas Torleiv Bronn ,  Jerry M. Chow ,  Markus Brink ,  Patryk Gumann ,  Daniela Florentina Bogorin

IPC: H05K7/20 ,  G06F30/20 ,  G06N10/00 ,  H01L21/265 ,  H01L23/31 ,  H01L23/32 ,  H01L31/02 ,  F28D21/00 ,  G06F113/20

Abstract: A thermalization structure is formed using a cover configured with a set of pillars, the cover being a part of a cryogenic enclosure of a low temperature device (LTD). A chip including the LTD is configured with a set of cavities, a cavity in the set of cavities having a cavity profile. A pillar from the set of pillars and corresponding to the cavity has a pillar profile such that the pillar profile causes the pillar to couple with the cavity of the cavity profile within a gap tolerance to thermally couple the chip to the cover for heat dissipation in a cryogenic operation of the chip.

公开(公告)号：US12052936B2

公开(公告)日：2024-07-30

申请号：US18148145

申请日：2022-12-29

Applicant: International Business Machines Corporation

Inventor： Devendra K. Sadana ,  Ning Li ,  Stephen W. Bedell ,  Sean Hart ,  Patryk Gumann

IPC: H10N60/80 ,  G06N10/00 ,  H10N60/10

CPC classification number: H10N60/805 ,  G06N10/00 ,  H10N60/128

Abstract: A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

公开(公告)号：US11777478B2

公开(公告)日：2023-10-03

申请号：US17548471

申请日：2021-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Salvatore Bernardo Olivadese ,  Patryk Gumann ,  Sean Hart ,  April Carniol

IPC: G06N10/20 ,  H03K5/1252 ,  H03K17/92

CPC classification number: H03K5/1252 ,  G06N10/20 ,  H03K17/92

Abstract: A quantum circuit includes a first qubit and a second qubit. A bus resonator transmission line is coupled between the first qubit and the second qubit. A readout bus is coupled to the first qubit. A switch is coupled to the bus resonator transmission line between the first qubit and the second qubit.

公开(公告)号：US20230252332A1

公开(公告)日：2023-08-10

申请号：US18055435

申请日：2022-11-15

Applicant: International Business Machines Corporation

Inventor： Nicholas T. Bronn ,  Patryk Gumann ,  Sean Hart ,  Salvatore B. Olivadese

IPC: G06N10/00 ,  H01P3/06 ,  H01P5/08

CPC classification number: G06N10/00 ,  H01P3/06 ,  H01P5/085

Abstract: A quantum computer includes a refrigeration system under vacuum including a containment vessel, a qubit chip contained within a refrigerated vacuum environment defined by the containment vessel. The quantum computer further includes a plurality of interior electromagnetic waveguides and a plurality of exterior electromagnetic waveguides. The quantum computer further includes a hermetic connector assembly operatively connecting the interior electromagnetic waveguides to the exterior electromagnetic waveguides while maintaining the refrigerated vacuum environment. The hermetic connector assembly includes an exterior multi-waveguide connector, an interior multi-waveguide connector, and a dielectric plate arranged between and hermetically sealed with the exterior multi-waveguide connector and the interior multi-waveguide connector. The dielectric plate permits electromagnetic energy when carried by the interior and exterior pluralities of electromagnetic waveguides to pass therethrough.

公开(公告)号：US11558955B2

公开(公告)日：2023-01-17

申请号：US16950610

申请日：2020-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Trevor Timpane ,  Layne A. Berge ,  Patryk Gumann ,  Sean Hart ,  Curtis Eugene Larsen ,  Michael Good

IPC: H05K1/02 ,  G06N10/00 ,  H01L39/04 ,  H05K1/09 ,  H05K1/18 ,  H05K3/02 ,  H05K3/32 ,  H05K1/11

Abstract: A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

公开(公告)号：US20220092459A1

公开(公告)日：2022-03-24

申请号：US17026245

申请日：2020-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniela Florentina Bogorin ,  Nicholas Torleiv Bronn ,  Patryk Gumann ,  Sean Hart ,  Salvatore Bernardo Olivadese

IPC: G06N10/00 ,  F25B9/12 ,  H01L39/22

Abstract: A quantum computing system includes a dilution refrigerator having a plurality of chambers. A trapped ion computing device includes a first set of qubits in a given chamber of the plurality of chambers of the dilution refrigerator. A superconducting computing device having a second set of superconducting qubits is inside the given chamber of the plurality of chambers of the dilution refrigerator.

公开(公告)号：US20210143311A1

公开(公告)日：2021-05-13

申请号：US16680078

申请日：2019-11-11

Applicant: International Business Machines Corporation

Inventor： Steven J. Holmes ,  Devendra K. Sadana ,  Sean Hart ,  Ning Li ,  Stephen W. Bedell ,  Patryk Gumann

IPC: H01L39/10 ,  H01L27/18

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A reflectrometry wire comprising a second metal within the reflectrometry region is formed. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

公开(公告)号：US20210143310A1

公开(公告)日：2021-05-13

申请号：US16680040

申请日：2019-11-11

Applicant: International Business Machines Corporation

Inventor： Steven J. Holmes ,  Devendra K. Sadana ,  Sean Hart ,  Stephen W. Bedell ,  Ning Li ,  Patryk Gumann

IPC: H01L39/10 ,  H01L27/18 ,  H01L39/24

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

公开(公告)号：US20210043823A1

公开(公告)日：2021-02-11

申请号：US16534882

申请日：2019-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Devendra K. Sadana ,  Ning Li ,  Stephen W. Bedell ,  Sean Hart ,  Patryk Gumann

IPC: H01L39/02 ,  H01L39/22 ,  G06N10/00

Abstract: A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

公开(公告)号：US20210028345A1

公开(公告)日：2021-01-28

申请号：US17061177

申请日：2020-10-01

Applicant: International Business Machines Corporation

Inventor： Sean Hart ,  Jay M. Gambetta ,  Patryk Gumann

IPC: H01L39/22 ,  H01L29/15 ,  H01L29/16 ,  H01L29/165 ,  H01L29/205 ,  H01L29/43 ,  H01L39/02 ,  H01L39/24

Abstract: A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.