Superconductor-semiconductor Josephson junction

    公开(公告)号:US12052936B2

    公开(公告)日:2024-07-30

    申请号:US18148145

    申请日:2022-12-29

    IPC分类号: H10N60/80 G06N10/00 H10N60/10

    摘要: A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

    HIGH DENSITY MICROWAVE HERMETIC INTERCONNECTS FOR QUANTUM APPLICATIONS

    公开(公告)号:US20230252332A1

    公开(公告)日:2023-08-10

    申请号:US18055435

    申请日:2022-11-15

    IPC分类号: G06N10/00 H01P3/06 H01P5/08

    CPC分类号: G06N10/00 H01P3/06 H01P5/085

    摘要: A quantum computer includes a refrigeration system under vacuum including a containment vessel, a qubit chip contained within a refrigerated vacuum environment defined by the containment vessel. The quantum computer further includes a plurality of interior electromagnetic waveguides and a plurality of exterior electromagnetic waveguides. The quantum computer further includes a hermetic connector assembly operatively connecting the interior electromagnetic waveguides to the exterior electromagnetic waveguides while maintaining the refrigerated vacuum environment. The hermetic connector assembly includes an exterior multi-waveguide connector, an interior multi-waveguide connector, and a dielectric plate arranged between and hermetically sealed with the exterior multi-waveguide connector and the interior multi-waveguide connector. The dielectric plate permits electromagnetic energy when carried by the interior and exterior pluralities of electromagnetic waveguides to pass therethrough.

    MAJORANA FERMION QUANTUM COMPUTING DEVICES WITH CHARGE SENSING FABRICATED WITH ION IMPLANT METHODS

    公开(公告)号:US20210143311A1

    公开(公告)日:2021-05-13

    申请号:US16680078

    申请日:2019-11-11

    IPC分类号: H01L39/10 H01L27/18

    摘要: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A reflectrometry wire comprising a second metal within the reflectrometry region is formed. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

    MAJORANA FERMION QUANTUM COMPUTING DEVICES FABRICATED WITH ION IMPLANT METHODS

    公开(公告)号:US20210143310A1

    公开(公告)日:2021-05-13

    申请号:US16680040

    申请日:2019-11-11

    IPC分类号: H01L39/10 H01L27/18 H01L39/24

    摘要: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

    SUPERCONDUCTOR-SEMICONDUCTOR JOSEPHSON JUNCTION

    公开(公告)号:US20210043823A1

    公开(公告)日:2021-02-11

    申请号:US16534882

    申请日:2019-08-07

    IPC分类号: H01L39/02 H01L39/22 G06N10/00

    摘要: A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

    High density microwave hermetic interconnects for quantum applications

    公开(公告)号:US11900217B2

    公开(公告)日:2024-02-13

    申请号:US18055435

    申请日:2022-11-15

    IPC分类号: G06N10/00 H01P3/06 H01P5/08

    CPC分类号: G06N10/00 H01P3/06 H01P5/085

    摘要: A quantum computer includes a refrigeration system under vacuum including a containment vessel, a qubit chip contained within a refrigerated vacuum environment defined by the containment vessel. The quantum computer further includes a plurality of interior electromagnetic waveguides and a plurality of exterior electromagnetic waveguides. The quantum computer further includes a hermetic connector assembly operatively connecting the interior electromagnetic waveguides to the exterior electromagnetic waveguides while maintaining the refrigerated vacuum environment. The hermetic connector assembly includes an exterior multi-waveguide connector, an interior multi-waveguide connector, and a dielectric plate arranged between and hermetically sealed with the exterior multi-waveguide connector and the interior multi-waveguide connector. The dielectric plate permits electromagnetic energy when carried by the interior and exterior pluralities of electromagnetic waveguides to pass therethrough.