公开(公告)号：US09404953B2

公开(公告)日：2016-08-02

申请号：US14068273

申请日：2013-10-31

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekharan Kothandaraman ,  John Matthew Safran ,  Timothy Dooling Sullivan

IPC: G01R27/26 ,  H01L21/66 ,  G01R31/28

CPC classification number: G01R27/2605 ,  G01R27/2617 ,  G01R31/2856 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34

Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.

Abstract translation: 本发明的实施例提供了用于检测位于紧邻3D集成芯片中的硅通孔（TSV）的后端行（BEOL）堆叠和BEOL结构中的异常的各种结构和方法。 检测到的异常可能包括将影响金属化连续性，金属层内的界面完整性，TSV放置的接近精度以及层间电介质完整性和金属化至TSV电介质完整性的应力，应变和损伤。 另外，这些结构彼此结合能够确定TSV的影响范围。 也就是说，BEV线（或通路）需要为TSV所影响的TSV的接近程度。

公开(公告)号：US20150115982A1

公开(公告)日：2015-04-30

申请号：US14068273

申请日：2013-10-31

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekharan Kothandaraman ,  John Matthew Safran ,  Timothy Dooling Sullivan

IPC: G01B7/00 ,  G01R27/26 ,  H01L21/66

CPC classification number: G01R27/2605 ,  G01R27/2617 ,  G01R31/2856 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34

Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.

Abstract translation: 本发明的实施例提供了用于检测位于紧邻3D集成芯片中的硅通孔（TSV）的后端行（BEOL）堆叠和BEOL结构中的异常的各种结构和方法。 检测到的异常可能包括将影响金属化连续性，金属层内的界面完整性，TSV放置的接近精度以及层间电介质完整性和金属化至TSV电介质完整性的应力，应变和损伤。 另外，这些结构彼此结合能够确定TSV的影响范围。 也就是说，BEV线（或通路）需要为TSV所影响的TSV的接近程度。

公开(公告)号：US08945955B2

公开(公告)日：2015-02-03

申请号：US13765772

申请日：2013-02-13

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

IPC: G01R31/26 ,  H01L21/66 ,  G11C13/00 ,  G11C13/04 ,  H01L45/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.

Abstract translation: 一种用于改变光电存储器件中的区域的反射率或电阻的方法。 改变该区域的反射率包括发送电流通过该区域以引起该区域中的反射率变化。 改变该区域的电阻包括：在区域上以第一光束强度投射激光束，导致区域从第一个不同的电阻值改变到第二个不同的电阻值; 电读取激光束携带的光信号具有第一数字值的第二电阻值; 在电读取第二电阻值之后，激光束在该区域上以第二光束强度投影，导致区域从第二电阻值变化到第一电阻值; 并且在激光束以第二光束强度投影在该区域上时电读取该区域的第一电阻值。

公开(公告)号：US20130258765A1

公开(公告)日：2013-10-03

申请号：US13765772

申请日：2013-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

IPC: G11C13/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.

Abstract translation: 一种用于改变光电存储器件中的区域的反射率或电阻的方法。 改变该区域的反射率包括发送电流通过该区域以引起该区域中的反射率变化。 改变该区域的电阻包括：在区域上以第一光束强度投射激光束，导致区域从第一个不同的电阻值改变到第二个不同的电阻值; 电读取激光束携带的光信号具有第一数字值的第二电阻值; 在电读取第二电阻值之后，激光束在该区域上以第二光束强度投影，导致区域从第二电阻值变化到第一电阻值; 并且在激光束以第二光束强度投影在该区域上时电读取该区域的第一电阻值。