公开(公告)号：US10900923B2

公开(公告)日：2021-01-26

申请号：US16655827

申请日：2019-10-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Carole D. Graas ,  Wen Liu ,  Prakash Periasamy

IPC: G01N27/22 ,  G01R27/26 ,  G01D5/24 ,  H03K17/955

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.

公开(公告)号：US20170263574A1

公开(公告)日：2017-09-14

申请号：US15606178

申请日：2017-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edward C. Cooney, III ,  Fen Chen ,  Jonathan M. Pratt ,  Jason P. Ritter ,  Patrick S. Spinney ,  Anna Tilley

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/573 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2224/11

Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

公开(公告)号：US09711464B2

公开(公告)日：2017-07-18

申请号：US14862700

申请日：2015-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edward C. Cooney, III ,  Fen Chen ,  Jonathan M. Pratt ,  Jason P. Ritter ,  Patrick S. Spinney ,  Anna Tilley

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/573 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2224/11

Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

公开(公告)号：US09613853B2

公开(公告)日：2017-04-04

申请号：US14883162

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Trevor A. Thompson ,  Eric J. White

IPC: H01L21/70 ,  H01L23/12 ,  H01L29/40 ,  H01L29/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/288

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20170084552A1

公开(公告)日：2017-03-23

申请号：US14862700

申请日：2015-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edward C. Cooney, III ,  Fen Chen ,  Jonathan M. Pratt ,  Jason P. Ritter ,  Patrick S. Spinney ,  Anna Tilley

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/573 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2224/11

Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

公开(公告)号：US09404953B2

公开(公告)日：2016-08-02

申请号：US14068273

申请日：2013-10-31

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekharan Kothandaraman ,  John Matthew Safran ,  Timothy Dooling Sullivan

IPC: G01R27/26 ,  H01L21/66 ,  G01R31/28

CPC classification number: G01R27/2605 ,  G01R27/2617 ,  G01R31/2856 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34

Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.

Abstract translation: 本发明的实施例提供了用于检测位于紧邻3D集成芯片中的硅通孔（TSV）的后端行（BEOL）堆叠和BEOL结构中的异常的各种结构和方法。 检测到的异常可能包括将影响金属化连续性，金属层内的界面完整性，TSV放置的接近精度以及层间电介质完整性和金属化至TSV电介质完整性的应力，应变和损伤。 另外，这些结构彼此结合能够确定TSV的影响范围。 也就是说，BEV线（或通路）需要为TSV所影响的TSV的接近程度。

公开(公告)号：US20150198654A1

公开(公告)日：2015-07-16

申请号：US14154505

申请日：2014-01-14

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Roger A. Dufresne ,  Kevin Kolvenbach ,  Michael A. Shinosky

IPC: G01R31/26

CPC classification number: G01R31/2623

Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.

Abstract translation: 公开了非平面场效应晶体管的测试结构和方法。 测试结构包括绝缘体层上的测试装置。 每个装置包括半导体鳍片。 每个翅片具有包括在一端的伪通道区域的第一部分和包括位于横向相邻于第一部分的扩散区域的第二部分。 具有侧壁间隔件的门可以与鳍的第一部分相邻。 第一接触可以在与鳍的端部相邻的绝缘体层上。 第二触点可以在鳍的第二部分上，使得栅极横向定位在触点之间。 将第一接触件偏压到栅极时进行的测量与第二接触件相对于栅极偏置时的测量值进行比较，以便评估栅极和第一接触件之间的横向电介质击穿，而与栅极绝缘击穿无关。

公开(公告)号：US10794948B2

公开(公告)日：2020-10-06

申请号：US15805377

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/66 ,  G01R31/08 ,  H01L23/48 ,  G01R31/28

Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

公开(公告)号：US10309919B2

公开(公告)日：2019-06-04

申请号：US16107544

申请日：2018-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Carole D. Graas ,  Wen Liu ,  Prakash Periasamy

IPC: G01N27/22 ,  G01R27/26 ,  G01D5/24 ,  H03K17/955

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.

公开(公告)号：US10126260B2

公开(公告)日：2018-11-13

申请号：US14706322

申请日：2015-05-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Carole D. Graas ,  Wen Liu ,  Prakash Periasamy

IPC: G01N27/22 ,  G01R27/26 ,  G01D5/24 ,  H03K17/955

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit.