公开(公告)号：US20090108299A1

公开(公告)日：2009-04-30

申请号：US11976590

申请日：2007-10-25

申请人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

发明人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7783

摘要： A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

摘要翻译： 半导体器件包括设置在漏极和源极区域之间以及阻挡层上方的T栅极，以形成与沟道层的肖特基接触。 第一非活性场缓和板设置在T栅极的一部分上方，并且第二有源场板设置在阻挡层上方和T栅极附近。

公开(公告)号：US07800132B2

公开(公告)日：2010-09-21

申请号：US11976590

申请日：2007-10-25

申请人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

发明人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7783

摘要： A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

摘要翻译： 半导体器件包括设置在漏极和源极区域之间以及阻挡层上方的T栅极，以形成与沟道层的肖特基接触。 第一非活性场缓和板设置在T栅极的一部分上方，并且第二有源场板设置在阻挡层上方和T栅极附近。

公开(公告)号：US20100184262A1

公开(公告)日：2010-07-22

申请号：US12659910

申请日：2010-03-25

申请人： Ioulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

发明人： Ioulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

IPC分类号： H01L21/335

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462

摘要： A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

摘要翻译： 半导体器件被制造为包括源极和漏极触点，其包括凹陷在阻挡层中的欧姆金属和沟道层的一部分; 保护介电层，设置在阻挡层上的源极和漏极接触之间; 设置在源极和保护电介质层之间以及保护电介质层和漏极接触之间的漏极和源极欧姆通孔中的金属化层; 以及设置在所述阻挡层上方的金属T型栅极，包括设置在所述金属T型栅极的杆的侧部上的场缓和板。

公开(公告)号：US07750370B2

公开(公告)日：2010-07-06

申请号：US12003098

申请日：2007-12-20

申请人： Ioulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

发明人： Ioulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462

摘要： A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

摘要翻译： 半导体器件被制造为包括源极和漏极触点，其包括凹陷在阻挡层中的欧姆金属和沟道层的一部分; 保护介电层，设置在阻挡层上的源极和漏极接触之间; 设置在源极和保护电介质层之间以及保护电介质层和漏极接触之间的漏极和源极欧姆通孔中的金属化层; 以及设置在所述阻挡层上方的金属T型栅极，包括设置在所述金属T型栅极的杆的侧部上的场缓和板。

公开(公告)号：US07897446B2

公开(公告)日：2011-03-01

申请号：US12659910

申请日：2010-03-25

申请人： Ioulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

发明人： Ioulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462

摘要： A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

摘要翻译： 半导体器件被制造为包括源极和漏极触点，其包括凹陷在阻挡层中的欧姆金属和沟道层的一部分; 保护介电层，设置在阻挡层上的源极和漏极接触之间; 设置在源极和保护电介质层之间以及保护电介质层和漏极接触之间的漏极和源极欧姆通孔中的金属化层; 以及设置在所述阻挡层上方的金属T型栅极，包括设置在所述金属T型栅极的杆的侧部上的场缓和板。

公开(公告)号：US20090267115A1

公开(公告)日：2009-10-29

申请号：US12150417

申请日：2008-04-28

申请人： Carol Osaka Namba ,  Po-Hsin Liu ,  Ioulia Smorchkova ,  Michael Wojtowicz ,  Robert Coffie ,  Yaochung Chen

发明人： Carol Osaka Namba ,  Po-Hsin Liu ,  Ioulia Smorchkova ,  Michael Wojtowicz ,  Robert Coffie ,  Yaochung Chen

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/42316 ,  H01L21/0272 ,  H01L21/0277 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.

摘要翻译： 一种制造具有球杆延伸部的T形门HEMT的方法，包括以下步骤：提供衬底; 在基板上提供双层抗蚀剂; 将双层抗蚀剂的区域暴露于电子束光刻，其中该区域对应于T形栅极开口; 将双层抗蚀剂的区域暴露于电子束光刻，其中该区域对应于球杆延伸部的形状，其中对应于球杆延伸部分的区域对于T形闸门的欧姆源侧为约1微米，大约为0.5微米 从T型门前方前进; 在对应于T型门开口的暴露区域中形成双层抗蚀剂; 在对应于俱乐部延伸的暴露区域中开发双层抗蚀剂; 以及通过金属化工艺形成T形门和球杆延伸。

公开(公告)号：US07608865B1

公开(公告)日：2009-10-27

申请号：US12150417

申请日：2008-04-28

申请人： Carol Osaka Namba ,  Po-Hsin Liu ,  Ioulia Smorchkova ,  Michael Wojtowicz ,  Robert Coffie ,  Yaochung Chen

发明人： Carol Osaka Namba ,  Po-Hsin Liu ,  Ioulia Smorchkova ,  Michael Wojtowicz ,  Robert Coffie ,  Yaochung Chen

IPC分类号： H01L31/092 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/42316 ,  H01L21/0272 ,  H01L21/0277 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.

摘要翻译： 一种制造具有球杆延伸部的T形门HEMT的方法，包括以下步骤：提供衬底; 在基板上提供双层抗蚀剂; 将双层抗蚀剂的区域暴露于电子束光刻，其中该区域对应于T形栅极开口; 将双层抗蚀剂的区域暴露于电子束光刻，其中该区域对应于球杆延伸部的形状，其中对应于球杆延伸部分的区域对于T形闸门的欧姆源侧为约1微米，大约为0.5微米 从T型门前方前进; 在对应于T型门开口的暴露区域中形成双层抗蚀剂; 在对应于俱乐部延伸的暴露区域中开发双层抗蚀剂; 以及通过金属化工艺形成T形门和球杆延伸。

公开(公告)号：US20090159930A1

公开(公告)日：2009-06-25

申请号：US12003098

申请日：2007-12-20

申请人： loulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

发明人： loulia Smorchkova ,  Robert Coffie ,  Ben Heying ,  Carol Namba ,  Po-Hsin Liu ,  Boris Hikin

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462

摘要： A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

摘要翻译： 半导体器件被制造为包括源极和漏极触点，其包括凹陷在阻挡层中的欧姆金属和沟道层的一部分; 保护介电层，设置在阻挡层上的源极和漏极接触之间; 设置在源极和保护电介质层之间以及保护电介质层和漏极接触之间的漏极和源极欧姆通孔中的金属化层; 以及设置在所述阻挡层上方的金属T型栅极，包括设置在所述金属T型栅极的杆的侧部上的场缓和板。

公开(公告)号：US08431962B2

公开(公告)日：2013-04-30

申请号：US11952527

申请日：2007-12-07

申请人： Benjamin Heying ,  Ioulia Smorchkova ,  Vincent Gambin ,  Robert Coffie

发明人： Benjamin Heying ,  Ioulia Smorchkova ,  Vincent Gambin ,  Robert Coffie

IPC分类号： H01L29/66

CPC分类号： H01L29/78 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66568 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00

摘要： A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.

摘要翻译： 提供减少的电子俘获和栅极电流泄漏的基于氮化物的FET器件。 该器件包括相对较厚的钝化层，以减少由器件处理引起的陷阱和栅极端子下方的薄钝化层，以减少栅极电流泄漏。 该器件包括沉积在衬底上的半导体器件层。 多个钝化层沉积在半导体器件层上，其中至少两个层由不同的介电材料制成以提供蚀刻停止。 可以使用层之间的界面作为蚀刻停止来去除一个或多个钝化层，使得可以严格控制栅极端子和半导体器件层之间的距离，其中可以使距离变得非常薄以增加器件性能 并减少栅极电流泄漏。

公开(公告)号：US20090146224A1

公开(公告)日：2009-06-11

申请号：US11952527

申请日：2007-12-07

申请人： Benjamin Heying ,  Ioulia Smorchkova ,  Vincent Gambin ,  Robert Coffie

发明人： Benjamin Heying ,  Ioulia Smorchkova ,  Vincent Gambin ,  Robert Coffie

IPC分类号： H01L21/76

CPC分类号： H01L29/78 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66568 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00

摘要： A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.

摘要翻译： 提供减少的电子俘获和栅极电流泄漏的基于氮化物的FET器件。 该器件包括相对较厚的钝化层，以减少由器件处理引起的陷阱和栅极端子下方的薄钝化层，以减少栅极电流泄漏。 该器件包括沉积在衬底上的半导体器件层。 多个钝化层沉积在半导体器件层上，其中至少两个层由不同的介电材料制成以提供蚀刻停止。 可以使用层之间的界面作为蚀刻停止来去除一个或多个钝化层，使得可以严格控制栅极端子和半导体器件层之间的距离，其中可以使距离变得非常薄以增加器件性能 并减少栅极电流泄漏。