公开(公告)号：US07800132B2

公开(公告)日：2010-09-21

申请号：US11976590

申请日：2007-10-25

申请人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

发明人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7783

摘要： A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

摘要翻译： 半导体器件包括设置在漏极和源极区域之间以及阻挡层上方的T栅极，以形成与沟道层的肖特基接触。 第一非活性场缓和板设置在T栅极的一部分上方，并且第二有源场板设置在阻挡层上方和T栅极附近。

公开(公告)号：US20070046520A1

公开(公告)日：2007-03-01

申请号：US11212570

申请日：2005-08-29

申请人： Spring Liu ,  Roger Tsai ,  Hao-Tai Hsieh ,  Sheng-Tang Chang ,  Wei-Kuang Chen ,  Yen-Chin Yang

发明人： Spring Liu ,  Roger Tsai ,  Hao-Tai Hsieh ,  Sheng-Tang Chang ,  Wei-Kuang Chen ,  Yen-Chin Yang

IPC分类号： H03M1/12

CPC分类号： G06F1/22 ,  G06F1/189 ,  G06F3/05 ,  H04L25/4917

摘要： An electronic circuit structure uses an analog-to-digital conversion concept for saving circuit pins and installs a control circuit on a main board, and the control circuit includes a processor, an analog-to-digital converter circuit, a power supply circuit and an ID generator circuit; wherein the power supply circuit is connected separately to the processor, the analog-to-digital converter circuit, and the ID generator circuit for providing a stable operating power supply; the analog-to-digital converter circuit is connected to the ID generator circuit for receiving a voltage divide power produced by the ID generator circuit and converting the voltage divide power into a digital machine ID; and the analog-to-digital converter circuit is connected to the processor for sending the machine ID. After the processor obtains the machine ID, the processor can analyze and determine the hardware configuration represented by the voltage divide power for the main board to carry out the booting operation.

摘要翻译： 电子电路结构使用模数转换概念来节省电路引脚并在主板上安装控制电路，并且控制电路包括处理器，模数转换器电路，电源电路和 ID发生器电路; 其中所述电源电路分别连接到所述处理器，所述模拟 - 数字转换器电路和所述ID发生器电路，用于提供稳定的工作电源; 模数转换器电路连接到ID发生器电路，用于接收由ID发生器电路产生的分压功率，并将分压功率转换成数字机器ID; 并且模数转换器电路连接到处理器以发送机器ID。 处理器获得机器ID后，处理器可以分析和确定主板分压功率所代表的硬件配置，进行启动操作。

公开(公告)号：US20050104216A1

公开(公告)日：2005-05-19

申请号：US10714966

申请日：2003-11-18

申请人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

发明人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

IPC分类号： B32B15/04 ,  C25D3/56 ,  C25D9/08 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

摘要翻译： 一种复合材料，其包含含有铜的层和在铜层上的电沉积CoWP膜。 CoWP膜含有11原子％至25原子％的磷并具有5nm至200nm的厚度。 本发明还涉及一种制造互连结构的方法，包括：在介电材料内提供沟槽或通孔，以及在沟槽或通孔内容纳铜的导电金属; 并通过电沉积在铜层上形成CoWP膜。 CoWP膜含有10原子％至25原子％的磷，并且具有5nm至200nm的厚度。 本发明还涉及包括与金属层接触的电介质层的互连结构; 金属层上的电沉积CoWP膜，CoWP膜上的铜层。

公开(公告)号：US20090108299A1

公开(公告)日：2009-04-30

申请号：US11976590

申请日：2007-10-25

申请人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

发明人： Ioulia Smorchkova ,  Carol Namba ,  Po-Hsin Liu ,  Robert Coffie ,  Roger Tsai

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7783

摘要： A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

摘要翻译： 半导体器件包括设置在漏极和源极区域之间以及阻挡层上方的T栅极，以形成与沟道层的肖特基接触。 第一非活性场缓和板设置在T栅极的一部分上方，并且第二有源场板设置在阻挡层上方和T栅极附近。

公开(公告)号：US20050127518A1

公开(公告)日：2005-06-16

申请号：US11047652

申请日：2005-02-02

申请人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

发明人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

IPC分类号： B32B15/04 ,  C25D3/56 ,  C25D9/08 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

公开(公告)号：US20050096964A1

公开(公告)日：2005-05-05

申请号：US10694737

申请日：2003-10-29

申请人： Roger Tsai

发明人： Roger Tsai

IPC分类号： G06Q10/00 ,  G06F17/60

CPC分类号： G06Q10/04 ,  G06Q10/08 ,  G06Q30/0202

摘要： A Best Indicator Adaptive (BIA) method fuses several singular indicators into one composite model to provide a new forecasting combination scheme. BIA uses the sizes of the spread of the distribution taking into account the variation of the distribution parameters themselves. Underlying the BIA method is the common theme and unifying theory of the power of quotient and the methods of making use of order composition and sales opportunities pipeline progression.

摘要翻译： 最佳指标自适应（BIA）方法将几个单一指标融合到一个复合模型中，以提供新的预测组合方案。 考虑到分布参数本身的变化，BIA使用分布扩展的大小。 BIA方法的基础是商人权力的共同主题和统一理论，以及利用订单构成和销售机会管道进展的方法。

公开(公告)号：US20060035467A1

公开(公告)日：2006-02-16

申请号：US10918119

申请日：2004-08-12

申请人： Peter Nam ,  Michael Lange ,  Roger Tsai

发明人： Peter Nam ,  Michael Lange ,  Roger Tsai

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L29/66462 ,  H01L21/30621 ,  H01L29/7783

摘要： Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30-42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.

摘要翻译： 锑基半导体器件形成在包括锑基缓冲层（24）和锑基缓冲帽（26）的衬底结构（10）上。 形成在衬底结构（10）上方的多个外延层（30-42）被干蚀刻以形成器件台面（12），并且缓冲帽（26）提供期望平滑的台面底板和围绕台面的电隔离。