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公开(公告)号：US20150074366A1
公开(公告)日：2015-03-12
申请号：US14024451
申请日：2013-09-11
CPC分类号： G06F9/467 , G06F9/30181 , G06F9/526 , G06F12/1466
摘要： An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.
摘要翻译： 一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。 例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。
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公开(公告)号：US20150277967A1
公开(公告)日：2015-10-01
申请号：US14225804
申请日：2014-03-26
摘要： In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.
摘要翻译： 在事务性存储器系统的实施例中，一种装置包括处理器和执行逻辑，以使得能够并行执行第一软件交易模式和第二软件交易模式的第二软件交易的至少一个第一软件交易，并且至少一个 第一硬件事务模式的硬件事务和第二硬件事务模式的至少一个第二硬件事务。 在一个示例中，执行逻辑可以在处理器内实现。 描述和要求保护其他实施例。
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3.发明授权公开(公告)号：US09639392B2
公开(公告)日：2017-05-02
申请号：US14108892
申请日：2013-12-17
摘要： A processing device implementing unbounded transactional memory with forward progress guarantees using a hardware global lock is disclosed. A processing device of the disclosure includes a hardware transactional memory (HTM) hardware contention manager to cause a bounded transaction to be translated to an unbounded transaction, the unbounded transaction to acquire a global hardware lock for the unbounded transaction, the global hardware lock read by bounded transactions that abort when the global hardware lock is taken. The processing device further includes an execution unit communicably coupled to the HTM hardware contention manager to execute instructions of the unbounded transaction without speculation, the unbounded transaction to release the global hardware lock upon completion of execution of the instructions.
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4.发明申请UNBOUNDED TRANSACTIONAL MEMORY WITH FORWARD PROGRESS GUARANTEES USING A HARDWARE GLOBAL LOCK 有权使用硬件全局锁定的前进进程保护的无关紧要的交易记忆公开(公告)号：US20150169362A1
公开(公告)日：2015-06-18
申请号：US14108892
申请日：2013-12-17
摘要： A processing device implementing unbounded transactional memory with forward progress guarantees using a hardware global lock is disclosed. A processing device of the disclosure includes a hardware transactional memory (HTM) hardware contention manager to cause a bounded transaction to be translated to an unbounded transaction, the unbounded transaction to acquire a global hardware lock for the unbounded transaction, the global hardware lock read by bounded transactions that abort when the global hardware lock is taken. The processing device further includes an execution unit communicably coupled to the HTM hardware contention manager to execute instructions of the unbounded transaction without speculation, the unbounded transaction to release the global hardware lock upon completion of execution of the instructions.
摘要翻译： 公开了一种使用硬件全局锁来实现具有前进进度的无界事务存储器的处理设备。 本公开的处理装置包括硬件事务存储器（HTM）硬件竞争管理器，用于使有界事务被转换为无界事务，该无界事务获取无界事务的全局硬件锁，全局硬件锁由 全局硬件锁定时中止的有界事务。 处理装置还包括执行单元，其可通信地耦合到HTM硬件争用管理器以执行无界事务的指令而无需推测，该无限制事务在完成指令的执行时释放全局硬件锁定。
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公开(公告)号：US20150100741A1
公开(公告)日：2015-04-09
申请号：US14129936
申请日：2013-07-15
IPC分类号： G06F9/46
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/067 , G06F3/0673 , G06F9/44 , G06F9/466 , G06F9/467 , G06F12/0813
摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.
摘要翻译： 描述了改进的事务性内存管理技术。 在一个实施例中，例如，设备可以包括处理器元件，用于由处理器元件执行以根据事务存储器进程同时执行软件事务和硬件事务的执行部件，用于由处理器元件执行的跟踪部件 激活全局锁以指示软件事务正在执行;以及最终化组件，用于由处理器元件执行以提交软件事务，并且在执行软件事务完成时停用全局锁定，终止组件中止硬件 当执行硬件事务完成时，全局锁活动时的事务。 描述和要求保护其他实施例。
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公开(公告)号：US20180129970A1
公开(公告)日：2018-05-10
申请号：US15348678
申请日：2016-11-10
CPC分类号： G06N3/0427 , G06N3/0454 , G06N3/08
摘要： A machine-learning decision system includes an online decision system and an offline decision system. The online decision system produces a first time slice-specific decision output corresponding to a first time slice based on one or more situational inputs received in the first time slice. The offline decision system produces a second Lime slice-specific decision output corresponding to the first time slice based on one or more situational inputs received in the first time slice and in a plurality of subsequent time slices occurring after the first time slice. The system further includes an online training system that conducts negative-reinforcement training of the online decision system in response to a nonconvergence between the first and the second time slice-specific decision outputs.
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7.发明申请公开(公告)号：US20140071144A1
公开(公告)日：2014-03-13
申请号：US14020616
申请日：2013-09-06
申请人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
IPC分类号： G06T1/60
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译： 一种促进异构平台中的共享指针的方法和装置。 在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的 处理核心。 异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。 通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。
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公开(公告)号：US08065491B2
公开(公告)日：2011-11-22
申请号：US11967232
申请日：2007-12-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3834 , G06F9/3863 , G06F9/466 , G06F9/52 , G06F9/522 , G06F12/0897 , G06F12/1027
摘要： A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
摘要翻译： 这里描述了用于为非事务写入提供优化的强原子性操作的方法和装置。 在初始非事务写入到存储器位置时获取锁定。 维护锁，直到检测到事件导致锁的释放。 结果，在获取和释放锁之间的中间期，通过不执行锁获取操作来加速对被锁定的存储器位置的任何后续写入。
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公开(公告)号：US20110271017A1
公开(公告)日：2011-11-03
申请号：US13182162
申请日：2011-07-13
IPC分类号： G06F5/14
CPC分类号： G06F12/0804 , G06F9/3834 , G06F9/3863 , G06F9/466 , G06F9/52 , G06F9/522 , G06F12/0897 , G06F12/1027
摘要： A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
摘要翻译： 这里描述了用于为非事务写入提供优化的强原子性操作的方法和装置。 在初始非事务写入到存储器位置时获取锁定。 维护锁，直到检测到事件导致锁的释放。 结果，在获取和释放锁之间的中间期，通过不执行锁获取操作来加速对锁定的存储器位置的任何后续写入。
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10.发明申请公开(公告)号：US20100162249A1
公开(公告)日：2010-06-24
申请号：US12344144
申请日：2008-12-24
IPC分类号： G06F9/46
CPC分类号： G06F9/466
摘要： A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.
摘要翻译： 这里描述了用于优化事务存储器系统中的静止的方法和装置。 标识非排序事务，例如只读事务，不访问非事务数据的事务和写缓冲硬件事务。 弱原子软件事务存储（STM）系统中的静止通过选择性应用静态来优化。 因此，事务可以与依赖于静态/等待以前的非排序事务相关联，以增加并行化并基于事务的序列化降低效率。
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