公开(公告)号：US20160179569A1

公开(公告)日：2016-06-23

申请号：US14581772

申请日：2014-12-23

Applicant: Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu

IPC: G06F9/46 ,  G06F9/45 ,  G06F9/30 ,  G06F12/08 ,  G06F9/445

CPC classification number: G06F9/467 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/44563 ,  G06F11/3632 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

Abstract: An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code; and a profiler to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code.

Abstract translation: 描述了用于硬件事务存储器（HTM）分析器的装置和方法。 例如，设备的一个实施例包括事务调试器（TDB）记录模块，用于记录与事务存储器程序代码的执行有关的数据，包括与事务存储器程序代码中的分支和事务事件的执行相关的数据; 以及分析器，用于使用基于跟踪的重放技术来分析记录数据的部分，以响应地生成包括事务级事件和可用于优化事务存储器程序代码的功能级冲突数据的简档数据。

公开(公告)号：US20150277968A1

公开(公告)日：2015-10-01

申请号：US14226312

申请日：2014-03-26

Applicant: Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

IPC: G06F9/46 ,  G06F11/36 ,  G11C7/10

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

Abstract translation: 公开了一种包括处理器和动态随机存取存储器（DRAM）的系统。 处理器包括包括硬件事务存储器（HTM）的混合事务处理存储器（HyTM），并且使用HyTM执行用于重放包括HTM指令并已被执行的程序的程序调试器。 程序调试器包括一个软件仿真器，通过仿真HTM来重播HTM指令。 公开和要求保护其他实施例。

公开(公告)号：US20140366006A1

公开(公告)日：2014-12-11

申请号：US13997786

申请日：2013-03-13

Applicant: Justin E. Gottschlich ,  Gilles A. Pokam ,  Cristiano L. Pereira ,  Klaus Danne ,  Shiliang Hu ,  Rolf Kassa

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Cristiano L. Pereira ,  Klaus Danne ,  Shiliang Hu ,  Rolf Kassa

IPC: G06F11/36 ,  G06T13/80

CPC classification number: G06F11/3664 ,  G06F9/38 ,  G06F11/323 ,  G06F11/3404 ,  G06F2201/865 ,  G06T11/206 ,  G06T13/80

Abstract: A system graphically visualizes performance and/or correctness features of a recorded execution of a multi-threaded software program. The system may process chunk-based information recorded during an execution of the multi-threaded program, prepare a graphical visualization of the recorded information, and display the graphical visualization on a display in an animated fashion. The system may allow a viewer to interactively control the display of the animated graphical visualization.

Abstract translation: 系统以图形方式可视化多线程软件程序的记录执行的性能和/或正确性特征。 系统可以处理在执行多线程程序期间记录的基于块的信息，准备所记录信息的图形可视化，并以动画方式在显示器上显示图形可视化。 系统可以允许观看者交互地控制动画图形可视化的显示。

公开(公告)号：US20180129970A1

公开(公告)日：2018-05-10

申请号：US15348678

申请日：2016-11-10

Applicant: Justin E. Gottschlich ,  Thijs Metsch ,  Leonard Truong ,  Tatiana Shpeisman ,  Sara S. Baghsorkhi

Inventor： Justin E. Gottschlich ,  Thijs Metsch ,  Leonard Truong ,  Tatiana Shpeisman ,  Sara S. Baghsorkhi

IPC: G06N99/00 ,  G06N5/04

CPC classification number: G06N3/0427 ,  G06N3/0454 ,  G06N3/08

Abstract: A machine-learning decision system includes an online decision system and an offline decision system. The online decision system produces a first time slice-specific decision output corresponding to a first time slice based on one or more situational inputs received in the first time slice. The offline decision system produces a second Lime slice-specific decision output corresponding to the first time slice based on one or more situational inputs received in the first time slice and in a plurality of subsequent time slices occurring after the first time slice. The system further includes an online training system that conducts negative-reinforcement training of the online decision system in response to a nonconvergence between the first and the second time slice-specific decision outputs.

公开(公告)号：US20150277967A1

公开(公告)日：2015-10-01

申请号：US14225804

申请日：2014-03-26

Applicant: Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

IPC: G06F9/46 ,  G06F12/10

CPC classification number: G06F9/467 ,  G06F9/528

Abstract: In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

Abstract translation: 在事务性存储器系统的实施例中，一种装置包括处理器和执行逻辑，以使得能够并行执行第一软件交易模式和第二软件交易模式的第二软件交易的至少一个第一软件交易，并且至少一个 第一硬件事务模式的硬件事务和第二硬件事务模式的至少一个第二硬件事务。 在一个示例中，执行逻辑可以在处理器内实现。 描述和要求保护其他实施例。

公开(公告)号：US20140007054A1

公开(公告)日：2014-01-02

申请号：US13535334

申请日：2012-06-27

Applicant: Youfeng Wu ,  Justin E. Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano L. Pereira

Inventor： Youfeng Wu ,  Justin E. Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano L. Pereira

IPC: G06F11/36

CPC classification number: G06F11/3688 ,  G06F8/70 ,  G06F11/36 ,  G06F11/3632

Abstract: Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

Abstract translation: 公开了在多线程程序中识别和再现并发错误的方法和系统。 本文公开的示例性方法包括定义数据类型。 数据类型包括与第一条件相关联的多线程程序的第一线程相关联的第一谓词，与多线程程序的第二线程相关联的第二谓词，第二谓词与第一谓词相关联 第二个条件和一个定义第一个谓词和第二个谓词之间的关系的表达式。 这种关系在满足时会导致并发错误被检测到。 符合数据类型的并发错误检测器用于检测多线程程序中的并发错误。

公开(公告)号：US09501340B2

公开(公告)日：2016-11-22

申请号：US13977690

申请日：2013-03-15

Applicant: Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

Inventor： Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

IPC: G06F9/45 ,  G06F11/07 ,  G06F9/38 ,  G06F11/14

CPC classification number: G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

Abstract translation: 描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。 如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。 第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。 记录系统可以记录第一和第二宏指令之间的交织。 该方法包括在发生时准确地重播第一和第二宏指令的交错记录。 正确重放可以包括重播第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

公开(公告)号：US20160232077A1

公开(公告)日：2016-08-11

申请号：US15026515

申请日：2013-12-12

Applicant: Shiliang HU ,  Gilles A. POKAM ,  Cristiano L. PEREIRA ,  Justin E. GOTTSCHLICH

Inventor： Shiliang HU ,  Gilles A. POKAM ,  Cristiano L. PEREIRA ,  Justin E. GOTTSCHLICH

IPC: G06F11/36

CPC classification number: G06F11/3632 ,  G06F9/526 ,  G06F11/0715 ,  G06F11/0778 ,  G06F11/30 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/366

Abstract: Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及通过检测与这种访问相关联的所选择的高速缓存事件的发生来检测由应用程序的不同部分的未协调数据访问引起的竞争条件。 一种装置包括处理器组件; 触发组件，用于由处理器组件执行以配置处理器组件的监控单元以检测与对一条数据的访问之间的竞争条件相关联的高速缓存事件，并且捕获处理器组件的状态的指示以生成监视 响应于缓存事件的发生的数据; 以及用于由处理器组件执行以配置监视单元的计数器的计数器组件，以使得能够以小于高速缓存事件的每次出现的频率捕获处理器组件的状态的指示。 描述和要求保护其他实施例。

公开(公告)号：US20150186178A1

公开(公告)日：2015-07-02

申请号：US14142475

申请日：2013-12-27

Applicant: Rolf Kassa ,  Justin E. Gottschlich ,  Shiliang Hu ,  Gilles A. Pokam ,  Robert C. Knauerhase

Inventor： Rolf Kassa ,  Justin E. Gottschlich ,  Shiliang Hu ,  Gilles A. Pokam ,  Robert C. Knauerhase

IPC: G06F9/46

CPC classification number: G06F9/467 ,  G06F9/528 ,  G06F11/0724 ,  G06F11/0772

Abstract: A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.

Abstract translation: 描述了一种处理器，其包括存储器访问冲突检测电路，以识别与正在由线程执行的事务有关的冲突，该线程相信它已经将信息锁定在存储器内。 如果存储器访问冲突检测电路识别导致事务中止的冲突，则处理器还包括记录电路来构造和报告数据包。

公开(公告)号：US20150074366A1

公开(公告)日：2015-03-12

申请号：US14024451

申请日：2013-09-11

Applicant: Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

IPC: G06F9/46 ,  G06F12/14

CPC classification number: G06F9/467 ,  G06F9/30181 ,  G06F9/526 ,  G06F12/1466

Abstract: An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.

Abstract translation: 一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。 例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。