公开(公告)号：US08410543B2

公开(公告)日：2013-04-02

申请号：US11965391

申请日：2007-12-27

申请人： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

发明人： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC分类号： H01L27/088

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.

摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和p +型的双层结构 沉积有高杂质浓度的多晶硅膜。

公开(公告)号：US20080185635A1

公开(公告)日：2008-08-07

申请号：US11965391

申请日：2007-12-27

申请人： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

发明人： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC分类号： H01L27/088

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.

摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜的双层结构， 具有沉积在其上的高杂质浓度的+ 型多晶硅膜。

公开(公告)号：US07863134B2

公开(公告)日：2011-01-04

申请号：US12695271

申请日：2010-01-28

申请人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

发明人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L29/4234 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/792

摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。

公开(公告)号：US07719051B2

公开(公告)日：2010-05-18

申请号：US12186488

申请日：2008-08-05

申请人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

发明人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

IPC分类号： H01L29/792

CPC分类号： H01L29/4234 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/792

摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。

公开(公告)号：US09318558B2

公开(公告)日：2016-04-19

申请号：US14413435

申请日：2012-07-09

申请人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

发明人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L29/06 ,  H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/1608 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/12 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7926

摘要： The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.

摘要翻译： 本发明是在使用SiC衬底的SiC-MOSFET功率器件中使高通道迁移率和高阈值电压共存。 在栅极绝缘膜上具有电荷陷阱特性的分层绝缘膜的SiC MOSFET在SiC MOSFET的沟道长度方向上具有不规则的阈值电压，特别是具有最小阈值电压的较短区域 通道长度方向与具有其它阈值电压的区域相比较。

公开(公告)号：US07682990B2

公开(公告)日：2010-03-23

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed.For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20050272198A1

公开(公告)日：2005-12-08

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed. For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20150179744A1

公开(公告)日：2015-06-25

申请号：US14413435

申请日：2012-07-09

申请人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

发明人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

IPC分类号： H01L29/16 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/1608 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/12 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7926

摘要： The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.

摘要翻译： 本发明是在使用SiC衬底的SiC-MOSFET功率器件中使高通道迁移率和高阈值电压共存。 在栅极绝缘膜上具有电荷陷阱特性的分层绝缘膜的SiC MOSFET在SiC MOSFET的沟道长度方向上具有不规则的阈值电压，特别是具有最小阈值电压的较短区域 通道长度方向与具有其它阈值电压的区域相比较。

公开(公告)号：US20150044840A1

公开(公告)日：2015-02-12

申请号：US14381597

申请日：2012-03-30

申请人： Keisuke Kobayashi ,  Toshiyuki Mine ,  Hirotaka Hamamura

发明人： Keisuke Kobayashi ,  Toshiyuki Mine ,  Hirotaka Hamamura

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/16

CPC分类号： H01L29/66477 ,  H01L21/02057 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/046 ,  H01L21/049 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7827

摘要： In order to provide a method for producing a SiC-MOSFET capable of increasing Vth without deteriorating channel mobility, before forming a gate insulation film, (a) silicon carbide substrate is oxidized by a low temperature oxidation method represented by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed.

摘要翻译： 为了提供能够增加Vth而不劣化沟道迁移率的SiC-MOSFET的制造方法，在形成栅极绝缘膜之前，（a）碳化硅衬底被等离子体氧化所代表的低温氧化法氧化，形成硅 氧化膜。 接下来，（b）去除氧化硅膜。 重复（a）和（b）工序一次以上后，（c）形成栅极绝缘膜。

公开(公告)号：US20090275183A1

公开(公告)日：2009-11-05

申请号：US12429236

申请日：2009-04-24

申请人： Toshiyuki Mine ,  Hirotaka Hamamura

发明人： Toshiyuki Mine ,  Hirotaka Hamamura

IPC分类号： H01L21/336 ,  H01L21/22 ,  H01L21/762

CPC分类号： H01L29/7833 ,  H01L21/76224 ,  H01L29/6659

摘要： A thermal oxidation method capable of obtaining a high oxidation rate by generating a sufficient enhanced-rate oxidation phenomenon even in a low temperature region is provided. In addition, a thermal oxidation method capable of forming a silicon oxide film having a high reliability even when formed at a low temperature region. A basic concept herein is to form a silicon oxide film by thermal reaction by generating a large amount of oxygen radicals (O*) having a large reactivity without using plasma. More specifically, ozone (O3) and other active gas are reacted, so that ozone (O3) is decomposed highly efficiently even in a low temperature region, thereby generating a large amount of oxygen radicals (O*). For example, a compound gas containing a halogen element can be used as the active gas.

摘要翻译： 提供了能够通过即使在低温区域产生足够的增强率氧化现象而能够获得高氧化率的热氧化法。 另外，即使在低温区域形成的情况下也能够形成具有高可靠性的氧化硅膜的热氧化法。 本文的基本概念是通过在不使用等离子体的情况下产生大量反应性的大量氧自由基（O *），通过热反应形成氧化硅膜。 更具体地，臭氧（O 3）和其它活性气体反应，使得即使在低温区域也高效地分解臭氧（O 3），从而产生大量的氧自由基（O *）。 例如，可以使用含有卤素元素的复合气体作为活性气体。